cnt32.vhd

来自「本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509）」· VHDL 代码 · 共 57 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT32 IS
	PORT
	(
		CLK:IN STD_LOGIC;
		SH,RS,ROG:OUT STD_LOGIC;		--Signals of CCD;PULSE:to PULSE1 and PULSE2 through a WIRE gat and a NOT gat; 
		PULSE,PULSE2:BUFFER STD_LOGIC
	);
END CNT32;
ARCHITECTURE A OF CNT32 IS
	SIGNAL Q: INTEGER RANGE 0 TO 29;
	SIGNAL NUM: INTEGER RANGE 0 TO 63899;
BEGIN
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
		CASE Q IS
			WHEN 16|17 =>
				RS<='1';
				SH<='0';
				Q<=Q+1;
			WHEN 20|21=>
				SH<='1';
				RS<='0';
				Q<=Q+1;
			WHEN 29 =>
				RS<='1';
				SH<='1';
				PULSE<=NOT PULSE;
				Q<=0;
			WHEN OTHERS =>
				RS<='1';
				SH<='1';
				Q<=Q+1;
			END CASE;
		END IF;
	END PROCESS;
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='0' THEN
			IF NUM=63899 THEN  NUM<=0;
			ELSE
				IF (NUM>1)AND(NUM<25) THEN
					ROG<='1';
				ELSE
					ROG<='0';
				END IF;
				NUM<=NUM+1;
			END IF;
		END IF;
	END PROCESS;
PULSE2<= NOT PULSE;
		   	
END A;