ilx509_driver.tan.rpt

本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509）

; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[0]    ; Q[2]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[1]    ; Q[2]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[3]    ; Q[2]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[2]    ; Q[2]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[4]    ; Q[2]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[0]    ; Q[3]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[1]    ; Q[3]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[3]    ; Q[3]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[2]    ; Q[3]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; NUM[0]  ; NUM[2]   ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; NUM[1]  ; NUM[2]   ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; NUM[2]  ; NUM[2]   ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[0]    ; Q[1]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; Q[1]    ; Q[1]     ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; NUM[0]  ; NUM[1]   ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; NUM[1]  ; NUM[1]   ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; NUM[0]  ; NUM[0]   ; CLK        ; CLK      ; None                        ; None                      ; 6.000 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 18.000 ns  ; LED~reg0    ; LED    ; CLK        ;
; N/A   ; None         ; 18.000 ns  ; PULSE2~reg0 ; PULSE  ; CLK        ;
; N/A   ; None         ; 10.000 ns  ; ROG~reg0    ; ROG    ; CLK        ;
; N/A   ; None         ; 10.000 ns  ; RS~reg0     ; RS     ; CLK        ;
; N/A   ; None         ; 10.000 ns  ; SH~reg0     ; SH     ; CLK        ;
; N/A   ; None         ; 10.000 ns  ; PULSE2~reg0 ; PULSE2 ; CLK        ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 29 09:54:17 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ILX509_Driver -c ILX509_Driver
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "ROG~reg0" as buffer
Info: Clock "CLK" has Internal fmax of 92.59 MHz between source register "NUM[1]" and destination register "ROG~reg0" (period= 10.8 ns)
    Info: + Longest register to register delay is 6.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 26; REG Node = 'NUM[1]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC56; Fanout = 1; COMB Node = 'ROG~13'
        Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 6.800 ns; Loc. = LC57; Fanout = 12; REG Node = 'ROG~reg0'
        Info: Total cell delay = 5.800 ns ( 85.29 % )
        Info: Total interconnect delay = 1.000 ns ( 14.71 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 6.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_37; Fanout = 25; CLK Node = 'CLK'
            Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC57; Fanout = 12; REG Node = 'ROG~reg0'
            Info: Total cell delay = 5.500 ns ( 84.62 % )
            Info: Total interconnect delay = 1.000 ns ( 15.38 % )
        Info: - Longest clock path from clock "CLK" to source register is 6.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_37; Fanout = 25; CLK Node = 'CLK'
            Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC32; Fanout = 26; REG Node = 'NUM[1]'
            Info: Total cell delay = 5.500 ns ( 84.62 % )
            Info: Total interconnect delay = 1.000 ns ( 15.38 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock "CLK" to destination pin "LED" through register "LED~reg0" is 18.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 14.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_37; Fanout = 25; CLK Node = 'CLK'
        Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC57; Fanout = 12; REG Node = 'ROG~reg0'
        Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = LC46; Fanout = 1; REG Node = 'LED~reg0'
        Info: Total cell delay = 12.500 ns ( 86.21 % )
        Info: Total interconnect delay = 2.000 ns ( 13.79 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC46; Fanout = 1; REG Node = 'LED~reg0'
        Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'LED'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Apr 29 09:54:18 2006
    Info: Elapsed time: 00:00:02