singt.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.all;

ENTITY lpm_rom0 IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END lpm_rom0;


ARCHITECTURE SYN OF lpm_rom0 IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);



	COMPONENT altsyncram--例化语句
	GENERIC (
		clock_enable_input_a		: STRING;
		clock_enable_output_a		: STRING;
		init_file		: STRING;
		intended_device_family		: STRING;
		lpm_hint		: STRING;
		lpm_type		: STRING;
		numwords_a		: NATURAL;
		operation_mode		: STRING;
		outdata_aclr_a		: STRING;
		outdata_reg_a		: STRING;
		widthad_a		: NATURAL;
		width_a		: NATURAL;
		width_byteena_a		: NATURAL
	);
	PORT (
			clock0	: IN STD_LOGIC ;
			address_a	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	q    <= sub_wire0(7 DOWNTO 0);

	altsyncram_component : altsyncram
	GENERIC MAP (
		clock_enable_input_a => "BYPASS",
		clock_enable_output_a => "BYPASS",
		init_file => "D:/SIN_GNT/DATEHEX/SDATE.HEX",
		intended_device_family => "Cyclone II",--参数传递映射
		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
		lpm_type => "altsyncram",--lpm类型
		numwords_a => 64,
		operation_mode => "ROM",
		outdata_aclr_a => "NONE",
		outdata_reg_a => "CLOCK0",
		widthad_a => 6,
		width_a => 8,
		width_byteena_a => 1
	)
	PORT MAP (
		clock0 => inclock,
		address_a => address,
		q_a => sub_wire0
	);



END SYN;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity singt is
port(clk : in std_logic;---信号源时钟
		 dout : out std_logic_vector(7 downto 0));---8位波形数据输出
end;
architecture dacc of singt is
component lpm_rom0 --调用波形数据存储器：lpm_rom0。vhdl声明
	port(address : in std_logic_vector (5 downto 0) ;--liuwei dizhi xinhao 
	     inclock : in std_logic;
		 		q: out std_logic_vector (7 downto 0));
end component;
	signal q1 : std_logic_vector (5 downto 0);
		begin
	process(clk)
		begin
	if clk'event and clk = '1' then q1<=q1+1;
	end if;
	end process;
	u1:lpm_rom0 port map(address=>q1,q=>dout,inclock=>clk);--例化
end;