prev_cmp_tel.tan.qmsg

手机号码归属地查询,代码详尽

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "N3\[2\] " "Info: Assuming node \"N3\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "H0\[0\] " "Info: Assuming node \"H0\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "H0\[3\] " "Info: Assuming node \"H0\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "H0\[2\] " "Info: Assuming node \"H0\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "H0\[1\] " "Info: Assuming node \"H0\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "N3\[1\] " "Info: Assuming node \"N3\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "N3\[3\] " "Info: Assuming node \"N3\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "N3\[0\] " "Info: Assuming node \"N3\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 1 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "addrr\[1\]~5608 " "Info: Detected gated clock \"addrr\[1\]~5608\" as buffer" {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "addrr\[1\]~5608" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "addrr\[1\]~6 " "Info: Detected gated clock \"addrr\[1\]~6\" as buffer" {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "addrr\[1\]~6" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 1 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "addrr\[4\] H1\[3\] N3\[2\] 5.616 ns register " "Info: tsu for register \"addrr\[4\]\" (data pin = \"H1\[3\]\", clock pin = \"N3\[2\]\") is 5.616 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.041 ns + Longest pin register " "Info: + Longest pin to register delay is 9.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.837 ns) 0.837 ns H1\[3\] 1 PIN PIN_Y13 13 " "Info: 1: + IC(0.000 ns) + CELL(0.837 ns) = 0.837 ns; Loc. = PIN_Y13; Fanout = 13; PIN Node = 'H1\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { H1[3] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.228 ns) 5.351 ns addrr\[5\]~5609 2 COMB LCCOMB_X21_Y1_N0 8 " "Info: 2: + IC(4.286 ns) + CELL(0.228 ns) = 5.351 ns; Loc. = LCCOMB_X21_Y1_N0; Fanout = 8; COMB Node = 'addrr\[5\]~5609'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.514 ns" { H1[3] addrr[5]~5609 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.356 ns) + CELL(0.228 ns) 5.935 ns addrr\[4\]~5616 3 COMB LCCOMB_X21_Y1_N28 1 " "Info: 3: + IC(0.356 ns) + CELL(0.228 ns) = 5.935 ns; Loc. = LCCOMB_X21_Y1_N28; Fanout = 1; COMB Node = 'addrr\[4\]~5616'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.584 ns" { addrr[5]~5609 addrr[4]~5616 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.272 ns) 6.755 ns addrr\[4\]~5620 4 COMB LCCOMB_X18_Y1_N28 1 " "Info: 4: + IC(0.548 ns) + CELL(0.272 ns) = 6.755 ns; Loc. = LCCOMB_X18_Y1_N28; Fanout = 1; COMB Node = 'addrr\[4\]~5620'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.820 ns" { addrr[4]~5616 addrr[4]~5620 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.206 ns) + CELL(0.225 ns) 7.186 ns addrr\[4\]~5621 5 COMB LCCOMB_X18_Y1_N6 1 " "Info: 5: + IC(0.206 ns) + CELL(0.225 ns) = 7.186 ns; Loc. = LCCOMB_X18_Y1_N6; Fanout = 1; COMB Node = 'addrr\[4\]~5621'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.431 ns" { addrr[4]~5620 addrr[4]~5621 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.627 ns) + CELL(0.228 ns) 9.041 ns addrr\[4\] 6 REG LCCOMB_X39_Y3_N0 26 " "Info: 6: + IC(1.627 ns) + CELL(0.228 ns) = 9.041 ns; Loc. = LCCOMB_X39_Y3_N0; Fanout = 26; REG Node = 'addrr\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.855 ns" { addrr[4]~5621 addrr[4] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.018 ns ( 22.32 % ) " "Info: Total cell delay = 2.018 ns ( 22.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.023 ns ( 77.68 % ) " "Info: Total interconnect delay = 7.023 ns ( 77.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.041 ns" { H1[3] addrr[5]~5609 addrr[4]~5616 addrr[4]~5620 addrr[4]~5621 addrr[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.041 ns" { H1[3] {} H1[3]~combout {} addrr[5]~5609 {} addrr[4]~5616 {} addrr[4]~5620 {} addrr[4]~5621 {} addrr[4] {} } { 0.000ns 0.000ns 4.286ns 0.356ns 0.548ns 0.206ns 1.627ns } { 0.000ns 0.837ns 0.228ns 0.228ns 0.272ns 0.225ns 0.228ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.482 ns + " "Info: + Micro setup delay of destination is 0.482 ns" {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "N3\[2\] destination 3.907 ns - Shortest register " "Info: - Shortest clock path from clock \"N3\[2\]\" to destination register is 3.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.827 ns) 0.827 ns N3\[2\] 1 CLK PIN_V11 6 " "Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_V11; Fanout = 6; CLK Node = 'N3\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { N3[2] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.053 ns) 1.724 ns addrr\[1\]~6 2 COMB LCCOMB_X18_Y1_N20 1 " "Info: 2: + IC(0.844 ns) + CELL(0.053 ns) = 1.724 ns; Loc. = LCCOMB_X18_Y1_N20; Fanout = 1; COMB Node = 'addrr\[1\]~6'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.897 ns" { N3[2] addrr[1]~6 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.054 ns) + CELL(0.000 ns) 2.778 ns addrr\[1\]~6clkctrl 3 COMB CLKCTRL_G5 6 " "Info: 3: + IC(1.054 ns) + CELL(0.000 ns) = 2.778 ns; Loc. = CLKCTRL_G5; Fanout = 6; COMB Node = 'addrr\[1\]~6clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.054 ns" { addrr[1]~6 addrr[1]~6clkctrl } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.225 ns) 3.907 ns addrr\[4\] 4 REG LCCOMB_X39_Y3_N0 26 " "Info: 4: + IC(0.904 ns) + CELL(0.225 ns) = 3.907 ns; Loc. = LCCOMB_X39_Y3_N0; Fanout = 26; REG Node = 'addrr\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.129 ns" { addrr[1]~6clkctrl addrr[4] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.105 ns ( 28.28 % ) " "Info: Total cell delay = 1.105 ns ( 28.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.802 ns ( 71.72 % ) " "Info: Total interconnect delay = 2.802 ns ( 71.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.907 ns" { N3[2] addrr[1]~6 addrr[1]~6clkctrl addrr[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.907 ns" { N3[2] {} N3[2]~combout {} addrr[1]~6 {} addrr[1]~6clkctrl {} addrr[4] {} } { 0.000ns 0.000ns 0.844ns 1.054ns 0.904ns } { 0.000ns 0.827ns 0.053ns 0.000ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.041 ns" { H1[3] addrr[5]~5609 addrr[4]~5616 addrr[4]~5620 addrr[4]~5621 addrr[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.041 ns" { H1[3] {} H1[3]~combout {} addrr[5]~5609 {} addrr[4]~5616 {} addrr[4]~5620 {} addrr[4]~5621 {} addrr[4] {} } { 0.000ns 0.000ns 4.286ns 0.356ns 0.548ns 0.206ns 1.627ns } { 0.000ns 0.837ns 0.228ns 0.228ns 0.272ns 0.225ns 0.228ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.907 ns" { N3[2] addrr[1]~6 addrr[1]~6clkctrl addrr[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.907 ns" { N3[2] {} N3[2]~combout {} addrr[1]~6 {} addrr[1]~6clkctrl {} addrr[4] {} } { 0.000ns 0.000ns 0.844ns 1.054ns 0.904ns } { 0.000ns 0.827ns 0.053ns 0.000ns 0.225ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 1 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "H0\[1\] addr\[30\] addrr\[5\] 10.414 ns register " "Info: tco from clock \"H0\[1\]\" to destination pin \"addr\[30\]\" through register \"addrr\[5\]\" is 10.414 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H0\[1\] source 4.699 ns + Longest register " "Info: + Longest clock path from clock \"H0\[1\]\" to source register is 4.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.837 ns) 0.837 ns H0\[1\] 1 CLK PIN_W11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.837 ns) = 0.837 ns; Loc. = PIN_W11; Fanout = 1; CLK Node = 'H0\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { H0[1] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.897 ns) + CELL(0.346 ns) 2.080 ns addrr\[1\]~5608 2 COMB LCCOMB_X18_Y1_N2 1 " "Info: 2: + IC(0.897 ns) + CELL(0.346 ns) = 2.080 ns; Loc. = LCCOMB_X18_Y1_N2; Fanout = 1; COMB Node = 'addrr\[1\]~5608'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.243 ns" { H0[1] addrr[1]~5608 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.231 ns) + CELL(0.225 ns) 2.536 ns addrr\[1\]~6 3 COMB LCCOMB_X18_Y1_N20 1 " "Info: 3: + IC(0.231 ns) + CELL(0.225 ns) = 2.536 ns; Loc. = LCCOMB_X18_Y1_N20; Fanout = 1; COMB Node = 'addrr\[1\]~6'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.456 ns" { addrr[1]~5608 addrr[1]~6 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.054 ns) + CELL(0.000 ns) 3.590 ns addrr\[1\]~6clkctrl 4 COMB CLKCTRL_G5 6 " "Info: 4: + IC(1.054 ns) + CELL(0.000 ns) = 3.590 ns; Loc. = CLKCTRL_G5; Fanout = 6; COMB Node = 'addrr\[1\]~6clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.054 ns" { addrr[1]~6 addrr[1]~6clkctrl } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.884 ns) + CELL(0.225 ns) 4.699 ns addrr\[5\] 5 REG LCCOMB_X18_Y1_N10 12 " "Info: 5: + IC(0.884 ns) + CELL(0.225 ns) = 4.699 ns; Loc. = LCCOMB_X18_Y1_N10; Fanout = 12; REG Node = 'addrr\[5\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.109 ns" { addrr[1]~6clkctrl addrr[5] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.633 ns ( 34.75 % ) " "Info: Total cell delay = 1.633 ns ( 34.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.066 ns ( 65.25 % ) " "Info: Total interconnect delay = 3.066 ns ( 65.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { H0[1] addrr[1]~5608 addrr[1]~6 addrr[1]~6clkctrl addrr[5] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { H0[1] {} H0[1]~combout {} addrr[1]~5608 {} addrr[1]~6 {} addrr[1]~6clkctrl {} addrr[5] {} } { 0.000ns 0.000ns 0.897ns 0.231ns 1.054ns 0.884ns } { 0.000ns 0.837ns 0.346ns 0.225ns 0.000ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.715 ns + Longest register pin " "Info: + Longest register to pin delay is 5.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addrr\[5\] 1 REG LCCOMB_X18_Y1_N10 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X18_Y1_N10; Fanout = 12; REG Node = 'addrr\[5\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { addrr[5] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.263 ns) + CELL(0.378 ns) 1.641 ns Mux90~32 2 COMB LCCOMB_X26_Y3_N8 2 " "Info: 2: + IC(1.263 ns) + CELL(0.378 ns) = 1.641 ns; Loc. = LCCOMB_X26_Y3_N8; Fanout = 2; COMB Node = 'Mux90~32'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.641 ns" { addrr[5] Mux90~32 } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 601 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.092 ns) + CELL(1.982 ns) 5.715 ns addr\[30\] 3 PIN PIN_A8 0 " "Info: 3: + IC(2.092 ns) + CELL(1.982 ns) = 5.715 ns; Loc. = PIN_A8; Fanout = 0; PIN Node = 'addr\[30\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.074 ns" { Mux90~32 addr[30] } "NODE_NAME" } } { "tel.vhd" "" { Text "D:/altera/quartus/电话号码所属地查找/tel.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.360 ns ( 41.29 % ) " "Info: Total cell delay = 2.360 ns ( 41.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.355 ns ( 58.71 % ) " "Info: Total interconnect delay = 3.355 ns ( 58.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.715 ns" { addrr[5] Mux90~32 addr[30] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.715 ns" { addrr[5] {} Mux90~32 {} addr[30] {} } { 0.000ns 1.263ns 2.092ns } { 0.000ns 0.378ns 1.982ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { H0[1] addrr[1]~5608 addrr[1]~6 addrr[1]~6clkctrl addrr[5] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { H0[1] {} H0[1]~combout {} addrr[1]~5608 {} addrr[1]~6 {} addrr[1]~6clkctrl {} addrr[5] {} } { 0.000ns 0.000ns 0.897ns 0.231ns 1.054ns 0.884ns } { 0.000ns 0.837ns 0.346ns 0.225ns 0.000ns 0.225ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.715 ns" { addrr[5] Mux90~32 addr[30] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.715 ns" { addrr[5] {} Mux90~32 {} addr[30] {} } { 0.000ns 1.263ns 2.092ns } { 0.000ns 0.378ns 1.982ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 1 0 "" 0 0}