tel.map.rpt

手机号码归属地查询,代码详尽

; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                              ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                 ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; tel.vhd                          ; yes             ; User VHDL File  ; D:/altera/quartus/电话号码所属地查找/tel.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 112   ;
; Dedicated logic registers                     ; 0     ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 46    ;
;                                               ;       ;
; Total combinational functions                 ; 112   ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 2     ;
;     -- 6 input functions                      ; 42    ;
;     -- 5 input functions                      ; 29    ;
;     -- 4 input functions                      ; 22    ;
;     -- <=3 input functions                    ; 17    ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 110   ;
;     -- extended LUT mode                      ; 2     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 158   ;
;                                               ;       ;
; Total registers                               ; 0     ;
;     -- Dedicated logic registers              ; 0     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 79    ;
;                                               ;       ;
; I/O pins                                      ; 78    ;
; Maximum fan-out node                          ; H2[2] ;
; Maximum fan-out                               ; 40    ;
; Total fan-out                                 ; 574   ;
; Average fan-out                               ; 3.02  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |tel                       ; 112 (112)         ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 78   ; 0            ; |tel                ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; addrr[0]                                           ; addrr[1]~6          ; yes                    ;
; addrr[1]                                           ; addrr[1]~6          ; yes                    ;
; addrr[2]                                           ; addrr[1]~6          ; yes                    ;
; addrr[3]                                           ; addrr[1]~6          ; yes                    ;
; addrr[4]                                           ; addrr[1]~6          ; yes                    ;
; addrr[5]                                           ; addrr[1]~6          ; yes                    ;
; Number of user-specified and inferred latches = 6  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Tue Oct 28 12:39:24 2008


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/altera/quartus/电话号码所属地查找/tel.map.smsg.