18_tech_lib.vhd

100个VHDL的例子

-------------------------
-- NAND4: 
--		4 Input NAND Gate
-------------------------
use work.types.all;
entity NAND4 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   O  : out bit);
end NAND4;

architecture FUNC of NAND4 is
begin
   O <= not (I1 and I2 and I3 and I4);
end FUNC;

-------------------------
-- NAND5: 
--		5 Input NAND Gate
-------------------------
use work.types.all;
entity NAND5 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   I5 : in  bit;
   O  : out bit);
end NAND5;

architecture FUNC of NAND5 is
begin
   O <= not (I1 and I2 and I3 and I4 and I5);
end FUNC;

-------------------------
-- OR2: 
--		2 Input OR Gate
-------------------------
use work.types.all;
entity OR2 is port(
   I1 : in  bit;
   I2 : in  bit;
   O  : out bit);
end OR2;

architecture FUNC of OR2 is
begin
   O <= I1 or I2;
end FUNC;

-------------------------
-- OR3: 
--		3 Input OR Gate
-------------------------
use work.types.all;
entity OR3 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   O  : out bit);
end OR3;

architecture FUNC of OR3 is
begin
   O <= I1 or I2 or I3;
end FUNC;

-------------------------
-- OR4: 
--		4 Input OR Gate
-------------------------
use work.types.all;
entity OR4 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   O  : out bit);
end OR4;

architecture FUNC of OR4 is
begin
   O <= I1 or I2 or I3 or I4;
end FUNC;

-------------------------
-- OR5: 
--		5 Input OR Gate
-------------------------
use work.types.all;
entity OR5 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   I5 : in  bit;
   O  : out bit);
end OR5;

architecture FUNC of OR5 is
begin
   O <= I1 or I2 or I3 or I4 or I5;
end FUNC;

-------------------------
-- NOR2: 
--		2 Input NOR Gate
-------------------------
use work.types.all;
entity NOR2 is port(
   I1 : in  bit;
   I2 : in  bit;
   O  : out bit);
end NOR2;

architecture FUNC of NOR2 is
begin
   O <= not (I1 or I2);
end FUNC;

-------------------------
-- NOR3: 
--		3 Input NOR Gate
-------------------------
use work.types.all;
entity NOR3 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   O  : out bit);
end NOR3;

architecture FUNC of NOR3 is
begin
   O <= not (I1 or I2 or I3);
end FUNC;

-------------------------
-- NOR4: 
--		4 Input NOR Gate
-------------------------
use work.types.all;
entity NOR4 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   O  : out bit);
end NOR4;

architecture FUNC of NOR4 is
begin
   O <= not (I1 or I2 or I3 or I4);
end FUNC;

-------------------------
-- NOR5: 
--		5 Input NOR Gate
-------------------------
use work.types.all;
entity NOR5 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   I5 : in  bit;
   O  : out bit);
end NOR5;

architecture FUNC of NOR5 is
begin
   O <= not (I1 or I2 or I3 or I4 or I5);
end FUNC;

-------------------------
-- XOR2: 
--		2 Input XOR Gate
-------------------------
use work.types.all;
entity XOR2 is port(
   I1 : in  bit;
   I2 : in  bit;
   O  : out bit);
end XOR2;

architecture FUNC of XOR2 is
begin
   O <= I1 xor I2;
end FUNC;

-------------------------
-- XOR3: 
--		3 Input XOR Gate
-------------------------
use work.types.all;
entity XOR3 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   O  : out bit);
end XOR3;

architecture FUNC of XOR3 is
begin
   O <= I1 xor I2 xor I3;
end FUNC;

-------------------------
-- XOR4: 
--		4 Input XOR Gate
-------------------------
use work.types.all;
entity XOR4 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   O  : out bit);
end XOR4;

architecture FUNC of XOR4 is
begin
   O <= I1 xor I2 xor I3 xor I4;
end FUNC;

-------------------------
-- XOR5: 
--		5 Input XOR Gate
-------------------------
use work.types.all;
entity XOR5 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   I5 : in  bit;
   O  : out bit);
end XOR5;

architecture FUNC of XOR5 is
begin
   O <= I1 xor I2 xor I3 xor I4 xor I5;
end FUNC;

-------------------------
-- XNOR2: 
--		2 Input XNOR Gate
-------------------------
use work.types.all;
entity XNOR2 is port(
   I1 : in  bit;
   I2 : in  bit;
   O  : out bit);
end XNOR2;

architecture FUNC of XNOR2 is
begin
   O <= not (I1 xor I2);
end FUNC;

-------------------------
-- XNOR3: 
--		3 Input XNOR Gate
-------------------------
use work.types.all;
entity XNOR3 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   O  : out bit);
end XNOR3;

architecture FUNC of XNOR3 is
begin
   O <= not (I1 xor I2 xor I3);
end FUNC;

-------------------------
-- XNOR4: 
--		4 Input XNOR Gate
-------------------------
use work.types.all;
entity XNOR4 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   O  : out bit);
end XNOR4;

architecture FUNC of XNOR4 is
begin
   O <= not (I1 xor I2 xor I3 xor I4);
end FUNC;

-------------------------
-- XNOR5: 
--		5 Input XNOR Gate
-------------------------
use work.types.all;
entity XNOR5 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   I5 : in  bit;
   O  : out bit);
end XNOR5;

architecture FUNC of XNOR5 is
begin
   O <= not (I1 xor I2 xor I3 xor I4 xor I5);
end FUNC;

---------------------------
-- INV: 
--		Inverter Primitive
---------------------------
use work.types.all;
entity INV is port(
   I : in  bit;
   O : out bit);
end INV;

architecture FUNC of INV is
begin
   O <= not I;
end FUNC;

--------------------------------------------------
-- The vhdl description for Xilinx Library (4000)
-- 
-- Category: Multiplexers
--
-- Yan.Zongfu
-- 1995.10.16
--------------------------------------------------

-------------------------
-- M2_1: 
--		2-to-1 Mux
-------------------------
use work.types.all;
entity M2_1 is port(
   D0 : in  bit;
   D1 : in  bit;
   O  : out bit;
   SE : in  bit);
end M2_1;

architecture FUNC of M2_1 is
begin
   O <= D0 when SE = '0' else
		D1;
end FUNC;

-------------------------
-- M4_1: 
--		4-to-1 Mux
-------------------------
use work.types.all;
entity M4_1 is port(
   D0 : in  bit;
   D1 : in  bit;
   D2 : in  bit;
   D3 : in  bit;
   O  : out bit;
   S0 : in  bit;
   S1 : in  bit);
end M4_1;

architecture FUNC of M4_1 is
begin
   O <= D0 when S1 = '0' and S0 = '0' else
   		D1 when S1 = '0' and S0 = '1' else
   		D2 when S1 = '1' and S0 = '0' else
   		D3;
end FUNC;

-------------------------
-- M8_1: 
--		8-to-1 Mux
-------------------------
use work.types.all;
entity M8_1 is port(
   D0 : in  bit;
   D1 : in  bit;
   D2 : in  bit;
   D3 : in  bit;
   D4 : in  bit;
   D5 : in  bit;
   D6 : in  bit;
   D7 : in  bit;
   O  : out bit;
   S0 : in  bit;
   S1 : in  bit;
   S2 : in  bit);
end M8_1;

architecture FUNC of M8_1 is
begin
   O <= D0 when S2 = '0' and S1 = '0' and S0 = '0' else
   		D1 when S2 = '0' and S1 = '0' and S0 = '1' else
   		D2 when S2 = '0' and S1 = '1' and S0 = '0' else
   		D3 when S2 = '0' and S1 = '1' and S0 = '1' else
   		D4 when S2 = '1' and S1 = '0' and S0 = '0' else
   		D5 when S2 = '1' and S1 = '0' and S0 = '1' else
   		D6 when S2 = '1' and S1 = '1' and S0 = '0' else
   		D7;
end FUNC;

-------------------------
-- M16_1: 
--		16-to-1 Mux
-------------------------
use work.types.all;
entity M16_1 is port(
   D0 : in  bit;
   D1 : in  bit;
   D2 : in  bit;
   D3 : in  bit;
   D4 : in  bit;
   D5 : in  bit;
   D6 : in  bit;
   D7 : in  bit;
   D8 : in  bit;
   D9 : in  bit;
   D10: in  bit;
   D11: in  bit;
   D12: in  bit;
   D13: in  bit;
   D14: in  bit;
   D15: in  bit;
   O  : out bit;
   S0 : in  bit;
   S1 : in  bit;
   S2 : in  bit;
   S3 : in  bit);
end M16_1;

architecture FUNC of M16_1 is
begin
   O <= D0  when S3 = '0' and S2 = '0' and S1 = '0' and S0 = '0' else
   		D1  when S3 = '0' and S2 = '0' and S1 = '0' and S0 = '1' else
   		D2  when S3 = '0' and S2 = '0' and S1 = '1' and S0 = '0' else
   		D3  when S3 = '0' and S2 = '0' and S1 = '1' and S0 = '1' else
   		D4  when S3 = '0' and S2 = '1' and S1 = '0' and S0 = '0' else
   		D5  when S3 = '0' and S2 = '1' and S1 = '0' and S0 = '1' else
   		D6  when S3 = '0' and S2 = '1' and S1 = '1' and S0 = '0' else
   		D7  when S3 = '0' and S2 = '1' and S1 = '1' and S0 = '1' else
   		D8  when S3 = '1' and S2 = '0' and S1 = '0' and S0 = '0' else
   		D9  when S3 = '1' and S2 = '0' and S1 = '0' and S0 = '1' else
   		D10 when S3 = '1' and S2 = '0' and S1 = '1' and S0 = '0' else
   		D11 when S3 = '1' and S2 = '0' and S1 = '1' and S0 = '1' else
   		D12 when S3 = '1' and S2 = '1' and S1 = '0' and S0 = '0' else
   		D13 when S3 = '1' and S2 = '1' and S1 = '0' and S0 = '1' else
   		D14 when S3 = '1' and S2 = '1' and S1 = '1' and S0 = '0' else
   		D15;
end FUNC;

--------------------------------------------------
-- The vhdl description for Xilinx Library (4000)
-- 
-- Category: Flip-Flops and Data Registers
--
-- Yan.Zongfu
-- 1995.10.17
--------------------------------------------------

------------------------------------------
-- FDRD: 
--		D Flip-Flop with CE/Dir, ResetDir
------------------------------------------
use work.types.all;
entity FDRD is port( 
		D  : in  bit;
		RD : in  bit;
		CE : in  bit;
		C  : in  bit;
		Q  : out bit);
end FDRD;

architecture FUNC of FDRD is
begin
   process
   begin
	  wait until C'event and C ='1';
	  if (CE = '1' and RD = '0') then
		 Q <= D;
      end if;
   end process;
end FUNC;

--------------------------------------------------
-- RD4: 
--		4-Bit Data Register with CE/Dir, ResetDir
--------------------------------------------------
use work.types.all;
entity RD4 is port( 
		D0 : in  bit;
		D1 : in  bit;
		D2 : in  bit;
		D3 : in  bit;
		RD : in  bit;
		CE : in  bit;
		C  : in  bit;
		Q0 : out bit;
		Q1 : out bit;
		Q2 : out bit;
		Q3 : out bit);
end RD4;

architecture FUNC of RD4 is
begin
   process
   begin
	  wait until C'event and C ='1';
	  if (CE = '1' and RD = '0') then
		 Q0 <= D0;
		 Q1 <= D1;
		 Q2 <= D2;
		 Q3 <= D3;
      end if;
   end process;
end FUNC;

--------------------------------------------------
-- RD8: 
--		8-Bit Data Register with CE/Dir, ResetDir
--------------------------------------------------
use work.types.all;
entity RD8 is port( 
		D0 : in  bit;
		D1 : in  bit;
		D2 : in  bit;
		D3 : in  bit;
		D4 : in  bit;
		D5 : in  bit;
		D6 : in  bit;
		D7 : in  bit;
		RD : in  bit;
		CE : in  bit;
		C  : in  bit;
		Q0 : out bit;
		Q1 : out bit;
		Q2 : out bit;
		Q3 : out bit;
		Q4 : out bit;
		Q5 : out bit;
		Q6 : out bit;
		Q7 : out bit);
end RD8;

architecture FUNC of RD8 is
begin
   process
   begin
	  wait until C'event and C ='1';
	  if (CE = '1' and RD = '0') then
		 Q0 <= D0;
		 Q1 <= D1;
		 Q2 <= D2;
		 Q3 <= D3;
		 Q4 <= D4;
		 Q5 <= D5;
		 Q6 <= D6;
		 Q7 <= D7;
      end if;
   end process;
end FUNC;

--------------------------------------------------
-- RD16: 
--		16-Bit Data Register with CE/Dir, ResetDir
--------------------------------------------------
use work.types.all;
entity RD16 is port( 
		D0 : in  bit;
		D1 : in  bit;
		D2 : in  bit;
		D3 : in  bit;
		D4 : in  bit;
		D5 : in  bit;
		D6 : in  bit;
		D7 : in  bit;
		D8 : in  bit;
		D9 : in  bit;
		D10: in  bit;
		D11: in  bit;
		D12: in  bit;
		D13: in  bit;
		D14: in  bit;
		D15: in  bit;
		RD : in  bit;
		CE : in  bit;
		C  : in  bit;
		Q0 : out bit;
		Q1 : out bit;
		Q2 : out bit;
		Q3 : out bit;
		Q4 : out bit;
		Q5 : out bit;
		Q6 : out bit;
		Q7 : out bit;
		Q8 : out bit;
		Q9 : out bit;
		Q10: out bit;
		Q11: out bit;
		Q12: out bit;
		Q13: out bit;
		Q14: out bit;
		Q15: out bit);
end RD16;

architecture FUNC of RD16 is
begin
   process
   begin
	  wait until C'event and C ='1';
	  if (CE = '1' and RD = '0') then
		 Q0  <= D0  ;
		 Q1  <= D1  ;
		 Q2  <= D2  ;
		 Q3  <= D3  ;
		 Q4  <= D4  ;
		 Q5  <= D5  ;
		 Q6  <= D6  ;
		 Q7  <= D7  ;
		 Q8  <= D8  ;
		 Q9  <= D9  ;
		 Q10 <= D10 ;
		 Q11 <= D11 ;
		 Q12 <= D12 ;
		 Q13 <= D13 ;
		 Q14 <= D14 ;
		 Q15 <= D15 ;
      end if;
   end process;
end FUNC;