18_tech_lib.vhd

100个VHDL的例子

------------------------------------
-- COMPM2: 
--		2-Bit Magnitude Comparator
------------------------------------
use work.types.all;
entity COMPM2 is port( 
		A0 : in  bit;
		A1 : in  bit;
		B0 : in  bit;
		B1 : in  bit;
		GT : out bit;
		LT : out bit);
end COMPM2;

architecture FUNC of COMPM2 is
begin
   process(A0,A1,B0,B1)
   begin
	  if (A0 = B0 and A1 = B1) then
		 GT <= '0';
		 LT <= '0';
	  elsif (A1 = B1 and A0 > B0) then 
		 GT <= '1';
		 LT <= '0';
	  elsif (A1 = B1 and A0 < B0) then 
		 GT <= '0';
		 LT <= '1';
	  elsif (A1 > B1) then 
		 GT <= '1';
		 LT <= '0';
	  elsif (A1 < B1) then 
		 GT <= '0';
		 LT <= '1';
      end if;
   end process;
end FUNC;

------------------------------------
-- COMP4: 
--		4-Bit Identity Comparator
------------------------------------
use work.types.all;
entity COMP4 is port( 
		A0 : in  bit;
		A1 : in  bit;
		A2 : in  bit;
		A3 : in  bit;
		B0 : in  bit;
		B1 : in  bit;
		B2 : in  bit;
		B3 : in  bit;
		EQ : out bit);
end COMP4;

architecture FUNC of COMP4 is
begin
   process(A0,A1,A2,A3,B0,B1,B2,B3)
   begin
	  if (A0 = B0 and A1 = B1 and A2 = B2 and A3 = B3) then
		 EQ <= '1';
	  else
		 EQ <= '0';
      end if;
   end process;
end FUNC;

------------------------------------
-- COMPM4: 
--		4-Bit Magnitude Comparator
------------------------------------
use work.types.all;
entity COMPM4 is port( 
		A0 : in  bit;
		A1 : in  bit;
		A2 : in  bit;
		A3 : in  bit;
		B0 : in  bit;
		B1 : in  bit;
		B2 : in  bit;
		B3 : in  bit;
		GT : out bit;
		LT : out bit);
end COMPM4;

architecture FUNC of COMPM4 is
begin
   process(A0, A1, A2, A3, B0, B1, B2, B3)
		variable A, B: bit_vector(3 downto 0);
		variable INT_A, INT_B: nat4;
   begin
		-- initial
		A := A3 & A2 & A1 & A0;
		B := B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- output
		if INT_A > INT_B then
		 	GT <= '1';
		 	LT <= '0';
		elsif INT_A < INT_B then
		 	GT <= '0';
		 	LT <= '1';
		else
		 	GT <= '0';
		 	LT <= '0';
		end if;
   end process;
end FUNC;

------------------------------------
-- COMP8: 
--		8-Bit Identity Comparator
------------------------------------
use work.types.all;
entity COMP8 is port( 
		A0 : in  bit;
		A1 : in  bit;
		A2 : in  bit;
		A3 : in  bit;
		A4 : in  bit;
		A5 : in  bit;
		A6 : in  bit;
		A7 : in  bit;
		B0 : in  bit;
		B1 : in  bit;
		B2 : in  bit;
		B3 : in  bit;
		B4 : in  bit;
		B5 : in  bit;
		B6 : in  bit;
		B7 : in  bit;
		EQ : out bit);
end COMP8;

architecture FUNC of COMP8 is
begin
   process(A0,A1,A2,A3,A4,A5,A6,A7, B0,B1,B2,B3,B4,B5,B6,B7)
		variable A, B: bit_vector(7 downto 0);
   begin
	  A := A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
	  B := B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;
	  if (A = B) then
		 EQ <= '1';
	  else
		 EQ <= '0';
      end if;
   end process;
end FUNC;

------------------------------------
-- COMPM8: 
--		8-Bit Magnitude Comparator
------------------------------------
use work.types.all;
entity COMPM8 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	LT : out bit;
	GT : out bit);
end COMPM8;  

architecture FUNC of COMPM8 is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7, B0,B1,B2,B3,B4,B5,B6,B7)
		variable A, B: bit_vector(7 downto 0);
		variable INT_A, INT_B: nat8;
	begin
		-- initial
		A := A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- output
		if INT_A > INT_B then
		 	GT <= '1';
		 	LT <= '0';
		elsif INT_A < INT_B then
		 	GT <= '0';
		 	LT <= '1';
		else
		 	GT <= '0';
		 	LT <= '0';
		end if;
	end process;
end FUNC;

------------------------------------
-- COMP16: 
--		16-Bit Identity Comparator
------------------------------------
use work.types.all;
entity COMP16 is port( 
		A0 : in  bit;
		A1 : in  bit;
		A2 : in  bit;
		A3 : in  bit;
		A4 : in  bit;
		A5 : in  bit;
		A6 : in  bit;
		A7 : in  bit;
		A8 : in  bit;
		A9 : in  bit;
		A10: in  bit;
		A11: in  bit;
		A12: in  bit;
		A13: in  bit;
		A14: in  bit;
		A15: in  bit;
		B0 : in  bit;
		B1 : in  bit;
		B2 : in  bit;
		B3 : in  bit;
		B4 : in  bit;
		B5 : in  bit;
		B6 : in  bit;
		B7 : in  bit;
		B8 : in  bit;
		B9 : in  bit;
		B10: in  bit;
		B11: in  bit;
		B12: in  bit;
		B13: in  bit;
		B14: in  bit;
		B15: in  bit;
		EQ : out bit);
end COMP16;

architecture FUNC of COMP16 is
begin
   process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10, A11,A12,A13,A14,A15,
	        B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10, B11,B12,B13,B14,B15)
		variable A, B: bit_vector(15 downto 0);
   begin
	  A := A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
	  B := B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;
	  if (A = B) then
		 EQ <= '1';
	  else
		 EQ <= '0';
      end if;
   end process;
end FUNC;

------------------------------------
-- COMPM16: 
--		16-Bit Magnitude Comparator
------------------------------------
use work.types.all;
entity COMPM16 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	A8 : in  bit;
	A9 : in  bit;
	A10: in  bit;
	A11: in  bit;
	A12: in  bit;
	A13: in  bit;
	A14: in  bit;
	A15: in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	B8 : in  bit;
	B9 : in  bit;
	B10: in  bit;
	B11: in  bit;
	B12: in  bit;
	B13: in  bit;
	B14: in  bit;
	B15: in  bit;
	LT : out bit;
	GT : out bit);
end COMPM16;  

architecture FUNC of COMPM16 is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,
			B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15)
		variable A, B: bit_vector(15 downto 0);
		variable INT_A, INT_B: nat16;
	begin
		-- initial
		A := A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- output
		if INT_A > INT_B then
		 	GT <= '1';
		 	LT <= '0';
		elsif INT_A < INT_B then
		 	GT <= '0';
		 	LT <= '1';
		else
		 	GT <= '0';
		 	LT <= '0';
		end if;
	end process;
end FUNC;

------------------------------------
-- COMP32: 
--		32-Bit Identity Comparator
------------------------------------
use work.types.all;
entity COMP32 is port( 
		A0 : in  bit;
		A1 : in  bit;
		A2 : in  bit;
		A3 : in  bit;
		A4 : in  bit;
		A5 : in  bit;
		A6 : in  bit;
		A7 : in  bit;
		A8 : in  bit;
		A9 : in  bit;
		A10: in  bit;
		A11: in  bit;
		A12: in  bit;
		A13: in  bit;
		A14: in  bit;
		A15: in  bit;
		A16: in  bit;
		A17: in  bit;
		A18: in  bit;
		A19: in  bit;
		A20: in  bit;
		A21: in  bit;
		A22: in  bit;
		A23: in  bit;
		A24: in  bit;
		A25: in  bit;
		A26: in  bit;
		A27: in  bit;
		A28: in  bit;
		A29: in  bit;
		A30: in  bit;
		A31: in  bit;
		B0 : in  bit;
		B1 : in  bit;
		B2 : in  bit;
		B3 : in  bit;
		B4 : in  bit;
		B5 : in  bit;
		B6 : in  bit;
		B7 : in  bit;
		B8 : in  bit;
		B9 : in  bit;
		B10: in  bit;
		B11: in  bit;
		B12: in  bit;
		B13: in  bit;
		B14: in  bit;
		B15: in  bit;
		B16: in  bit;
		B17: in  bit;
		B18: in  bit;
		B19: in  bit;
		B20: in  bit;
		B21: in  bit;
		B22: in  bit;
		B23: in  bit;
		B24: in  bit;
		B25: in  bit;
		B26: in  bit;
		B27: in  bit;
		B28: in  bit;
		B29: in  bit;
		B30: in  bit;
		B31: in  bit;
		EQ : out bit);
end COMP32;

architecture FUNC of COMP32 is
begin
   process (A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,
		    A11,A12,A13,A14,A15,A16,A17,A18,A19,A20,
	        A21,A22,A23,A24,A25,A25,A27,A28,A29,A30, A31,
	        B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,
		    B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,
	        B21,B22,B23,B24,B25,B25,B27,B28,B29,B30, B31)
		variable A, B: bit_vector(31 downto 0);
   begin
	  A := A31 & A30 & A29 & A28 & A27 & A26 & A25 & A24 & A23 & A22 & A21 & A20 & A19 & A18 & A17 & A16 & A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
	  B := B31 & B30 & B29 & B28 & B27 & B26 & B25 & B24 & B23 & B22 & B21 & B20 & B19 & B18 & B17 & B16 & B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;
	  if (A = B) then
		 EQ <= '1';
	  else
		 EQ <= '0';
      end if;
   end process;
end FUNC;

------------------------------------
-- COMPM32: 
--		32-Bit Magnitude Comparator
------------------------------------
use work.types.all;
entity COMPM32 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	A8 : in  bit;
	A9 : in  bit;
	A10: in  bit;
	A11: in  bit;
	A12: in  bit;
	A13: in  bit;
	A14: in  bit;
	A15: in  bit;
	A16: in  bit;
	A17: in  bit;
	A18: in  bit;
	A19: in  bit;
	A20: in  bit;
	A21: in  bit;
	A22: in  bit;
	A23: in  bit;
	A24: in  bit;
	A25: in  bit;
	A26: in  bit;
	A27: in  bit;
	A28: in  bit;
	A29: in  bit;
	A30: in  bit;
	A31: in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	B8 : in  bit;
	B9 : in  bit;
	B10: in  bit;
	B11: in  bit;
	B12: in  bit;
	B13: in  bit;
	B14: in  bit;
	B15: in  bit;
	B16: in  bit;
	B17: in  bit;
	B18: in  bit;
	B19: in  bit;
	B20: in  bit;
	B21: in  bit;
	B22: in  bit;
	B23: in  bit;
	B24: in  bit;
	B25: in  bit;
	B26: in  bit;
	B27: in  bit;
	B28: in  bit;
	B29: in  bit;
	B30: in  bit;
	B31: in  bit;
	LT : out bit;
	GT : out bit);
end COMPM32;  

architecture FUNC of COMPM32 is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,
		    A11,A12,A13,A14,A15,A16,A17,A18,A19,A20,
	        A21,A22,A23,A24,A25,A25,A27,A28,A29,A30, A31,
	        B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,
		    B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,
	        B21,B22,B23,B24,B25,B25,B27,B28,B29,B30, B31)
		variable A, B: bit_vector(31 downto 0);
		variable INT_A, INT_B: integer;
	begin
		-- initial
		A := A31 & A30 & A29 & A28 & A27 & A26 & A25 & A24 & A23 & A22 & A21 & A20 & A19 & A18 & A17 & A16 & A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B31 & B30 & B29 & B28 & B27 & B26 & B25 & B24 & B23 & B22 & B21 & B20 & B19 & B18 & B17 & B16 & B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- output
		if INT_A > INT_B then
		 	GT <= '1';
		 	LT <= '0';
		elsif INT_A < INT_B then
		 	GT <= '0';
		 	LT <= '1';
		else
		 	GT <= '0';
		 	LT <= '0';
		end if;
	end process;
end FUNC;

--------------------------------------------------
-- The vhdl description for Xilinx Library (4000)
-- 
-- Category: Gates
--
-- Yan.Zongfu
-- 1995.10.16
--------------------------------------------------

-------------------------
-- AND2: 
--		2 Input AND Gate
-------------------------
use work.types.all;
entity AND2 is port(
   I1 : in  bit;
   I2 : in  bit;
   O  : out bit);
end AND2;

architecture FUNC of AND2 is
begin
   O <= I1 and I2;
end FUNC;

-------------------------
-- AND3: 
--		3 Input AND Gate
-------------------------
use work.types.all;
entity AND3 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   O  : out bit);
end AND3;

architecture FUNC of AND3 is
begin
   O <= I1 and I2 and I3;
end FUNC;

-------------------------
-- AND4: 
--		4 Input AND Gate
-------------------------
use work.types.all;
entity AND4 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   O  : out bit);
end AND4;

architecture FUNC of AND4 is
begin
   O <= I1 and I2 and I3 and I4;
end FUNC;

-------------------------
-- AND5: 
--		5 Input AND Gate
-------------------------
use work.types.all;
entity AND5 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   I4 : in  bit;
   I5 : in  bit;
   O  : out bit);
end AND5;

architecture FUNC of AND5 is
begin
   O <= I1 and I2 and I3 and I4 and I5;
end FUNC;

-------------------------
-- NAND2: 
--		2 Input NAND Gate
-------------------------
use work.types.all;
entity NAND2 is port(
   I1 : in  bit;
   I2 : in  bit;
   O  : out bit);
end NAND2;

architecture FUNC of NAND2 is
begin
   O <= not (I1 and I2);
end FUNC;

-------------------------
-- NAND3: 
--		3 Input NAND Gate
-------------------------
use work.types.all;
entity NAND3 is port(
   I1 : in  bit;
   I2 : in  bit;
   I3 : in  bit;
   O  : out bit);
end NAND3;

architecture FUNC of NAND3 is
begin
   O <= not (I1 and I2 and I3);
end FUNC;