📄 a.vhd
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--Steps needed by SDRAM to Maintain data Ends
--##############################################################################
-- Process: This process increments a counter to get a 100 us delay
-- as needed by the dram for initialization. After it is
-- done, this counter is used to generate the scheduled
-- auto refereshes which must be done once every 7.81 us
-- This counter will just let know everybody that this
-- time is over and ONE auto_referesh is scheduled. It is
-- the responsibility of some other block to collect this
-- info and actually produce the auto refereshes signals
-- Since it is not required that it is MUST to perform
-- auto referesh @ 7.81 rate, since all the 8192 bursts of
-- auto refresh could be done at once, it is decided that
-- the number of auto refereshes will be scheduled, and
-- once the up is done with its current READ WRITE
-- operation, the number of auto refereshes sheduled will
-- be performed, all at once. Since this code will support
-- page burst mode, it is anticipated, that the up may
-- keep a READ or WRITE asserted > 7.81 us in worst case
--##############################################################################
init_delay_reg: PROCESS(clk_in)
BEGIN
IF(RISING_EDGE(clk_in)) THEN
IF(reset = '1') THEN
delay_reg <= (others => '0');
one_auto_ref_time_done <= '0';
ELSE
IF(reset_del_count = '1') THEN
delay_reg <= (others => '0');
--it is imp that in the following elsif, dram_init_done_s_del
--is considered instead of dram_init_done_s because the event
--following this should ensure that reset_del_count has no
--activity thereafter
--in case we use dram_init_done_s signal, then we are not sure
--that reset_del_count has done its job, we want to make suer
--that reset_del_count has done its job before 'delay_reg'
--counter can be used to generate the 7.81 us stuff
--and since dram_init_done_s_del is guranteed to come after
--reset_del_count, it is safe to use it in followine elsif
ELSIF(dram_init_done_s_del = '1') THEN
IF(to_integer(unsigned(delay_reg)) = auto_ref_co) THEN
--it means that the delay_reg has counted enough i.e 780 clocks
--and we are ready to schedule a referesh
delay_reg <= (others => '0');
one_auto_ref_time_done <= '1';
ELSE
delay_reg <= incr_vec(delay_reg);
one_auto_ref_time_done <= '0';
END IF;
ELSE
delay_reg <= incr_vec(delay_reg);
one_auto_ref_time_done <= '0';
END IF; --(reset_del_count = '1')
END IF; --(reset = '1')
END IF; --(RISING_EDGE(clk_in))
END PROCESS init_delay_reg;
--##############################################################################
-- Process:
--##############################################################################
init_auto_ref_count_reg: PROCESS(clk_in)
BEGIN
IF(RISING_EDGE(clk_in)) THEN
no_of_refs_needed <= (others => '0');
IF(reset = '1') THEN
ELSE
IF(dram_init_done_s = '1') THEN
IF(no_of_refs_needed = "1111111111") THEN
no_of_refs_needed <= no_of_refs_needed;
ELSE
--auto_ref_tim_done will be '1' for one clock cycle just
--after 780 clocks
IF(one_auto_ref_time_done = '1') THEN
no_of_refs_needed <= incr_vec(no_of_refs_needed);
ELSIF(one_auto_ref_complete = '1') THEN
--it must be checked if my some means tht no_of_refs_needed
--counter is going below 0, that means it is an error
--however it is commented at present to run the sims as now
--IF(no_of_refs_needed = "0000000000") THEN
-- no_of_refs_needed <= no_of_refs_needed;
--ELSE
no_of_refs_needed <= dcr_vec(no_of_refs_needed);
--END IF;
END IF;
END IF;
END IF; --IF(dram_init_done_s = '1') THEN
END IF; --(reset = '1')
END IF; --(RISING_EDGE(clk_in))
END PROCESS init_auto_ref_count_reg;
--##############################################################################
-- Process:
--##############################################################################
init_reg: PROCESS(clk_in)
BEGIN
IF(RISING_EDGE(clk_in)) THEN
IF(reset = '1') THEN
dram_init_done_s <= '0';
command_bus <= inhibit;
one_auto_ref_complete <= '0';
rd_wr_just_terminated <= '0';
addr_sig <= (others => '0');
ba_sig <= (others => '0');
ELSE
IF(dram_init_done_s = '0') THEN
----------------------------------------------------
--dram init starts
----------------------------------------------------
IF(to_integer(unsigned(delay_reg)) = sd_init) THEN
dram_init_done_s <= dram_init_done_s;
command_bus <= precharge;
one_auto_ref_complete <= one_auto_ref_complete;
rd_wr_just_terminated <= rd_wr_just_terminated;
addr_sig <= (others => '0');
addr_sig(10) <= '1';
ba_sig <= ba_sig;
ELSIF(to_integer(unsigned(delay_reg)) = sd_init + trp) THEN
dram_init_done_s <= dram_init_done_s;
command_bus <= auto_ref;
one_auto_ref_complete <= one_auto_ref_complete;
rd_wr_just_terminated <= rd_wr_just_terminated;
addr_sig <= (others => '0');
ba_sig <= ba_sig;
ELSIF(to_integer(unsigned(delay_reg))
= sd_init + trp + trfc ) THEN
dram_init_done_s <= dram_init_done_s;
command_bus <= auto_ref;
one_auto_ref_complete <= one_auto_ref_complete;
rd_wr_just_terminated <= rd_wr_just_terminated;
addr_sig <= (others => '0');
ba_sig <= ba_sig;
ELSIF(to_integer(unsigned(delay_reg)) =
sd_init + trp + 2*trfc ) THEN
dram_init_done_s <= dram_init_done_s;
command_bus <= load_mode_reg;
one_auto_ref_complete <= one_auto_ref_complete;
rd_wr_just_terminated <= rd_wr_just_terminated;
addr_sig <= (others => '0');
addr_sig(11 downto 0) <= mod_reg_val;
ba_sig <= ba_sig;
ELSIF(to_integer(unsigned(delay_reg)) =
sd_init + trp + 2*trfc + tmrd) THEN
dram_init_done_s <= '1';
command_bus <= nop;
one_auto_ref_complete <= one_auto_ref_complete;
rd_wr_just_terminated <= rd_wr_just_terminated;
addr_sig <= (others => '0');
ba_sig <= ba_sig;
ELSE
dram_init_done_s <= dram_init_done_s;
command_bus <= nop;
dram_init_done_s <= dram_init_done_s;
one_auto_ref_complete <= one_auto_ref_complete;
rd_wr_just_terminated <= rd_wr_just_terminated;
addr_sig <= (others => '0');
addr_sig(10) <= addr_sig(10);
ba_sig <= ba_sig;
END IF;
----------------------------------------------------
--dram init is done
----------------------------------------------------
----------------------------------------------------
--dram write
----------------------------------------------------
--The following two lines together suggest that the
--write operation is just started. Therefore a active
--command is issued immediately
--IT is V.IMP to note that a row can be made active
--upon the rd or wr request form up ONLY when the
--previous operation is OVER. OVER means, the
--bank related to previous access has been PRECHARGED
--which is known here by rd_wr_just_terminated signal
--this signal goes '1' just after a request fom up to
--put rd/wr over, and it goes back to '0', when
--precharge is finished.
ELSIF((wr_n_from_up = '0') AND (rd_wr_just_terminated = '0'))THEN
IF(wr_n_from_up_del_1 = '1') THEN -- means a pulse on
-- +ive eged of wr_n
ba_sig <= addr_from_up(23 downto 22) ;
command_bus <= active;
--address organisation at present
--23 downto 22 are bank selectors, total banks = 4
--21 downto 9 are row selectors, total rows = 8192
--9 downto 0 are col selectors, total cols = 512
--total space available 4 x 8192 x 512 = 16 Meg
--the following need attention, as it is using hard coded
--numbers, should be made functions of generics declared
--above ################
addr_sig <= addr_from_up(21 downto 9) ;
ELSIF(to_integer(unsigned(small_count)) = trcd) THEN
ba_sig <= addr_from_up(23 downto 22) ;
command_bus <= write;
addr_sig(8 downto 0) <= addr_from_up(8 downto 0) ;
ELSE
ba_sig <= ba_sig;
command_bus <= rd_wr_in_prog; --dqm is 00 else its a NOP
addr_sig <= addr_sig;
END IF;
----------------------------------------------------
--dram write Ends
----------------------------------------------------
----------------------------------------------------
--dram read
----------------------------------------------------
ELSIF((rd_n_from_up = '0') AND (rd_wr_just_terminated = '0'))THEN
IF(wr_n_from_up_del_1 = '1') THEN
ba_sig <= addr_from_up(23 downto 22) ;
command_bus <= active;
addr_sig <= addr_from_up(21 downto 9) ;
ELSIF(to_integer(unsigned(small_count)) = trcd) THEN
ba_sig <= ba_sig;
command_bus <= read;
addr_sig(8 downto 0) <= addr_from_up(8 downto 0) ;
ELSE
ba_sig <= ba_sig;
command_bus <= rd_wr_in_prog; --dqm is 00 else its a NOP
addr_sig <= addr_sig;
END IF;
----------------------------------------------------
--dram read Ends
----------------------------------------------------
----------------------------------------------------
--Burst Terminate when rd or wr operation finishes
--It is to be noted that the signal
--wr_from_up_del_1 is a function of rd_from_up_as well
--so while wr_n_from_up = 1 or rd_n_from_up = 1, and
--_del_1 signal is 0, it means that its a +ive edge on
--either wr_n or rd_n meaning as termination of read/write
--request from the up
----------------------------------------------------
ELSIF((wr_n_from_up = '1' OR rd_n_from_up = '1')
AND (wr_n_from_up_del_1 = '0')) THEN
command_bus <= burst_terminate;
rd_wr_just_terminated <= '1';
ELSIF(rd_wr_just_terminated = '1') THEN
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