a.vhd

ASIC Design using VHDL by Shyam Mani

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

--TOP ENTITY NAME : dramcntrl
--ARCHITECTURE NAME : rtl

ENTITY dramcntrl IS
    GENERIC (
            del : integer := 15; -- will be used to scale the 100 us counter
            len_auto_ref : integer := 10; -- will be used to count no of 
                                          -- pending auto refs which are needed
            len_small : integer := 8; -- will be used to count times for trc,
                                       --tRFC t..etc..etc after INIT has been
                                       --done
            addr_bits_to_dram : integer := 13;
            addr_bits_from_up : integer := 24;
            ba_bits : integer := 2 
            );

    PORT (
        --dram pins Starts

        addr  : OUT    STD_LOGIC_VECTOR (addr_bits_to_dram - 1 DOWNTO 0) ;
        ba    : OUT    STD_LOGIC_VECTOR (ba_bits - 1 DOWNTO 0);
        clk   : OUT    STD_LOGIC ;
        cke   : OUT    STD_LOGIC ;
        cs_n  : OUT    STD_LOGIC ;
        ras_n : OUT    STD_LOGIC ;
        cas_n : OUT    STD_LOGIC ;
        we_n  : OUT    STD_LOGIC ;
        dqm   : OUT    STD_LOGIC_VECTOR (1 DOWNTO 0) ;
        --dram pins Ends
        

        --clk and reset signals Starts
        clk_in : IN STD_LOGIC;
        reset  : IN STD_LOGIC;
        --clk and reset signals Ends
	
	--dram_control_pins at up IF Starts
        addr_from_up : IN STD_LOGIC_VECTOR (addr_bits_from_up -1 DOWNTO 0) ;
        rd_n_from_up : IN STD_LOGIC ;
        wr_n_from_up : IN STD_LOGIC ;
        bus_term_from_up : IN STD_LOGIC ;
        dram_init_done  : OUT STD_LOGIC ;
        rd_dat_from_dram_ready : OUT STD_LOGIC ; -- needs more consideration
        dram_busy : OUT STD_LOGIC 
	--dram_control_pins at up IF Ends
	
      
        );

END dramcntrl;

--##############################################################################
--Architecture starts here
--##############################################################################

ARCHITECTURE rtl OF dramcntrl IS


--##############################################################################
--The following function increments an std_logic_vector type by '1'
--typical usage next_count <= incr_vec(next_count);
--when count reaches the highest value(all ones), the next count is zero.
--##############################################################################

--Function Declaration Section 
FUNCTION incr_vec(s1:STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is 
                  --this function increments a STD_LOGIC_VECTOR type by '1' 
        VARIABLE V : STD_LOGIC_VECTOR(s1'high DOWNTO s1'low) ; 
        VARIABLE tb : STD_LOGIC_VECTOR(s1'high DOWNTO s1'low); 
        BEGIN 
        tb(s1'low) := '1'; 
        V := s1; 
        for i in (V'low + 1) to V'high loop 
            tb(i) := V(i - 1) and tb(i -1); 
        end loop; 
        for i in V'low to V'high loop 
            if(tb(i) = '1') then 
                V(i) := not(V(i)); 
            end if; 
        end loop; 
        return V; 
        end incr_vec; -- end function 

--##############################################################################
--The following function decrements an std_logic_vector type by '1'
--typical usage next_count <= incr_vec(next_count);
--when count reaches the lowest value(all zeros), the next count is all ones.
--##############################################################################

        FUNCTION  dcr_vec(s1:std_logic_vector) return std_logic_vector is
                  --this function decrements a std_logic_vector type by '1'
        VARIABLE V : std_logic_vector(s1'high downto s1'low) ;
        VARIABLE tb : std_logic_vector(s1'high downto s1'low);
        BEGIN
        tb(s1'low) := '0';
        V := s1;
        for i in (V'low + 1) to V'high loop
            tb(i) := V(i - 1) or tb(i -1);
        end loop;
        for i in V'low to V'high loop
            if(tb(i) = '0') then
                V(i) := not(V(i));
            end if;
        end loop;
        return V;
        end dcr_vec; -- end function


--Function Declaration Section Ends


--Signal Declaration Section

  --SIGNAL delay_reg_int : integer range 0 to 2**14 -1 ;
  SIGNAL delay_reg : STD_LOGIC_VECTOR( del - 1 downto 0) ;
  SIGNAL addr_sig  : STD_LOGIC_VECTOR (addr_bits_to_dram - 1 DOWNTO 0) ;
  SIGNAL ba_sig    : STD_LOGIC_VECTOR(ba_bits - 1 DOWNTO 0) ;

  SIGNAL dram_init_done_s   : STD_LOGIC ;
  SIGNAL dram_init_done_s_del   : STD_LOGIC ;
  SIGNAL reset_del_count   : STD_LOGIC ; --it will reset the delay counter
  --when the dram is ready so that the delay counter now becomes the counter
  --which will count for auto refereshes i.e 7.81 us

  SIGNAL command_bus   : STD_LOGIC_VECTOR (5 DOWNTO 0) ;
  --bit 5 = cs
  --bit 4 = ras
  --bit 3 = cas
  --bit 2 = we
  --bit 1 = dqm(1)
  --bit 0 = dqm(0)

  SIGNAL no_of_refs_needed   : STD_LOGIC_VECTOR(len_auto_ref - 1 downto 0) ;
  SIGNAL one_auto_ref_time_done   : STD_LOGIC ;
  SIGNAL one_auto_ref_complete: STD_LOGIC ;

  SIGNAL auto_ref_pending : STD_LOGIC ;
  SIGNAL write_req_pending: STD_LOGIC ;

  SIGNAL small_count: STD_LOGIC_VECTOR(len_small - 1 downto 0) ;
  SIGNAL small_all_zeros: STD_LOGIC;

  SIGNAL wr_n_from_up_del_1: STD_LOGIC;--to produce a pulse on wr_n_form_up
  SIGNAL wr_n_from_up_del_2: STD_LOGIC;--to produce a pulse on wr_n_form_up
  SIGNAL wr_n_from_up_pulse: STD_LOGIC;--to pulsed wr_n_form_up

  --SIGNAL wr_active_done: STD_LOGIC;--to know if active command has been issued
                                   --following a write sequence
  SIGNAL en_path_up_to_dram: STD_LOGIC;--en direction of data flwo up->dram
  SIGNAL en_path_dram_to_up: STD_LOGIC;--en direction of data flwo dram->up

  SIGNAL rd_wr_just_terminated: STD_LOGIC;--It will logg the status that rd or 
                              --write is just terminated. and and auto precharge 
                              --is needed.It is here to let autoprecharge be done
  SIGNAL dram_busy_sig : STD_LOGIC;--means that dram is doing auto_ref cycle.

--Signal Declaration Section Ends

--Constants Declaration Section
  CONSTANT mod_reg_val     : std_logic_vector(11 downto 0) := "000000100111";
  -- ll,10 = reserved, 
  -- 9 = '0' programmed burst length, Burst len applicable for rd and wr both 
  -- 8,7 = Op mode = 00
  -- 6,5,4 = CAS latency = 010 = cas latency of 2 
  -- 3 = Burst Type = '0' = Sequential
  -- 2,1,0 = Brust Length = 111 = Full Page Brust

  CONSTANT sd_init     : integer := 10000; -- = 1000 * f in MHz 
  CONSTANT trp         : integer := 4;     -- = 20 ns (20 ns < (trp - 1)* T);
  CONSTANT trfc        : integer := 8;     -- = 66 ns (66 ns < (trfc - 1)* T);
  CONSTANT tmrd        : integer := 3;     -- = 2 Wait time after Mode reg prog
  CONSTANT trcd        : integer := 2;     -- = 15 ns (15 ns < (trcd)*T)
                         --trcd is the time which must be consumed after the 
                         --issuence of ACTIVE and before any other command can
                         --be issued

  CONSTANT auto_ref_co : integer := 780;   -- = auto_ref_co > 7.81 * F in MHz

---------------------------------------------------------------rc-dd
--------------------------------------------------------------caawqq
--------------------------------------------------------------sssemm
  CONSTANT inhibit         : std_logic_vector(5 downto 0) := "111111";
  CONSTANT nop             : std_logic_vector(5 downto 0) := "011111";
  CONSTANT active          : std_logic_vector(5 downto 0) := "001111";
  CONSTANT read            : std_logic_vector(5 downto 0) := "010100"; --tbd
  CONSTANT write           : std_logic_vector(5 downto 0) := "010000"; --tbd
  CONSTANT burst_terminate : std_logic_vector(5 downto 0) := "011011";
  CONSTANT precharge       : std_logic_vector(5 downto 0) := "001011";
  CONSTANT auto_ref        : std_logic_vector(5 downto 0) := "000111";
  CONSTANT load_mode_reg   : std_logic_vector(5 downto 0) := "000011";

  CONSTANT read_high_byte  : std_logic_vector(5 downto 0) := "011111"; --tbd
  CONSTANT read_low_byte   : std_logic_vector(5 downto 0) := "011111"; --tbd
  CONSTANT write_high_byte : std_logic_vector(5 downto 0) := "011111"; --tbd
  CONSTANT write_low_byte  : std_logic_vector(5 downto 0) := "011111"; --tbd

  CONSTANT rd_wr_in_prog   : std_logic_vector(5 downto 0) := "011100"; --tbd
  --the above constant signifies that a read or wirte burst is in progress
  --dqms are 00 else it is a NOP

--Constants Declaration Section Ends

BEGIN

--Steps needed by SDRAM to intitialize

--#1. Power up initialization time taken 100 us, one, either NOP or INHIBIT
--    Command is MUST within this period -- as per specs

--#2. PRECHARGE Command MUST be issued

--#3. 2 AUTO REFRESH cycles MUST be performed

--#4. Mode Register may be programmed now.

--Steps needed by SDRAM to initialize Ends

--Steps needed by SDRAM to write data

--#1). Get the address from up, store the address, Activate the corresponding
--     Row. by providing A0 to A12(which will select the ROW) and BA0, BA1
--     which will select the Coloumn
--
--#2). Wait for trcd = 15 ns  while putting NOP on the command bus
--     provide  A0 through A9, A11 in case of (x4), A0 through A9 in case of
--     (x8) , A0 through A8 in case of (x16). We will use (x8)
--#3). Issue the Coloumn address with the choice of A10 = 0 for Disable Auto
--     Precharge, A10 = 1 for Enable Auto Precharge.We will use Auto Precharge
--     DISABLED But here in case of Burst length = full page we do not need
--     A10 functiionality since it is not used in this cycle.

--Steps needed by SDRAM to write data Ends


--Steps needed by SDRAM to Maintain data

--The SDRAM MUST be AUTO REFERESHED every 7.81 us or 7810 ns
--if f is the clock freq, then T = 1/f, so n * 1/F = 7810,so n=7.81*f in MHz
--Here f = 100 MHz, so n = 781. Every 781 clocks, an Auto Ref is needed.
--It may be possible, to apply 8192 Auto refs Once in 64 ms or Once in
--64000 * f in HHz clock cycles, we take f  100 MHz, so every 6400000 clock 
--cycles, we need a burst of 8192 Auto refereshs