📄 lcnt8.sim.rpt
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The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+
; |lcnt8|a[7] ; |lcnt8|a[7] ; out ;
; |lcnt8|a[6] ; |lcnt8|a[6] ; out ;
; |lcnt8|a[5] ; |lcnt8|a[5] ; out ;
; |lcnt8|a[4] ; |lcnt8|a[4] ; out ;
; |lcnt8|a[3] ; |lcnt8|a[3] ; out ;
; |lcnt8|a[2] ; |lcnt8|a[2] ; out ;
; |lcnt8|a[1] ; |lcnt8|a[1] ; out ;
; |lcnt8|a[0] ; |lcnt8|a[0] ; out ;
; |lcnt8|b[7] ; |lcnt8|b[7] ; out ;
; |lcnt8|b[6] ; |lcnt8|b[6] ; out ;
; |lcnt8|b[5] ; |lcnt8|b[5] ; out ;
; |lcnt8|lcnt:inst1|count[7] ; |lcnt8|lcnt:inst1|count[7] ; out ;
; |lcnt8|lcnt:inst|count[6] ; |lcnt8|lcnt:inst|count[6] ; out ;
; |lcnt8|lcnt:inst|count[5] ; |lcnt8|lcnt:inst|count[5] ; out ;
; |lcnt8|lcnt:inst|count[4] ; |lcnt8|lcnt:inst|count[4] ; out ;
; |lcnt8|lcnt:inst|count[3] ; |lcnt8|lcnt:inst|count[3] ; out ;
; |lcnt8|lcnt:inst|count[7] ; |lcnt8|lcnt:inst|count[7] ; out ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0]~0 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0]~0 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~1 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~1 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~2 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~2 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7]~1 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7]~1 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[6] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[6] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[5] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[5] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[4] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[4] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[3] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[3] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[2] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[2] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[1] ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[1] ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[7]~1 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[7]~1 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[6]~2 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[6]~2 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[5]~3 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[5]~3 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[4]~4 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[4]~4 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[3]~5 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[3]~5 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~4 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~4 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~5 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~5 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~6 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~6 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~7 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~7 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~8 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~8 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~9 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~9 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~10 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~10 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~11 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~11 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~12 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~12 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~13 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~13 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~14 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~14 ; out0 ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~15 ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~15 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0]~0 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0]~0 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~1 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~1 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~2 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~2 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7]~1 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7]~1 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[6] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[6] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[5] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[5] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[4] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[4] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[3] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[3] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[2] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[2] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[1] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[1] ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7]~1 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7]~1 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~4 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~4 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~5 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~5 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~6 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~6 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~7 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~7 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~8 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~8 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~9 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~9 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~10 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~10 ; out0 ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~11 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~11 ; out0 ;
+---------------------------------------------------------------------------+---------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Mar 31 21:41:33 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off lcnt8 -c lcnt8
Info: Overwriting simulation input file with simulation results
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 68.84 %
Info: Number of transitions in simulation is 315275
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Mar 31 21:41:35 2008
Info: Elapsed time: 00:00:02
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