lcnt8.sim.rpt

这个是用VHDL实现的正负脉宽调制器

; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[3]~5             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[3]~5                  ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[2]~6             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[2]~6                  ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[1]~7             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[1]~7                  ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7]               ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7]                    ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6]               ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6]                    ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5]               ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5]                    ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[4]               ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[4]                    ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[3]               ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[3]                    ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[2]               ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[1]               ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~12                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~12                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~13                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~13                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~14                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~14                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~15                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~15                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~16                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~16                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~17                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~17                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~18                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~18                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~19                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~19                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~20                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~20                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~21                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~21                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~22                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~22                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~23                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~23                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~24                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~24                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~25                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~25                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~26                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~26                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~27                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~27                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~28                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~28                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~29                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~29                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~30                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~30                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~31                            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~31                                 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; sout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6]      ; cout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; sout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5]      ; cout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; sout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; sout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                         ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------------+
; Node Name                                                             ; Output Port Name                                                      ; Output Port Type ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------------+
; |lcnt8|a[7]                                                           ; |lcnt8|a[7]                                                           ; out              ;
; |lcnt8|a[6]                                                           ; |lcnt8|a[6]                                                           ; out              ;
; |lcnt8|a[5]                                                           ; |lcnt8|a[5]                                                           ; out              ;
; |lcnt8|a[4]                                                           ; |lcnt8|a[4]                                                           ; out              ;
; |lcnt8|a[3]                                                           ; |lcnt8|a[3]                                                           ; out              ;
; |lcnt8|a[2]                                                           ; |lcnt8|a[2]                                                           ; out              ;
; |lcnt8|a[1]                                                           ; |lcnt8|a[1]                                                           ; out              ;
; |lcnt8|a[0]                                                           ; |lcnt8|a[0]                                                           ; out              ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0]~0  ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0]~0  ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[0]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~1              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~1              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~2              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~2              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7]~1  ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7]~1  ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[7]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[6]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[6]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[5]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[5]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[4]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[4]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[3]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[3]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[2]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[2]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[1]    ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|datab_node[1]    ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~4              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~4              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~5              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~5              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~6              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~6              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~7              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~7              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~8              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~8              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~9              ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~9              ; out0             ;
; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~10             ; |lcnt8|lcnt:inst|lpm_add_sub:add_rtl_1|addcore:adder|_~10             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0]~0 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0]~0 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[0]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~1             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~1             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~2             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~2             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7]~1 ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7]~1 ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[7]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[6]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[6]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[5]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[5]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[4]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[4]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[3]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[3]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[2]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[2]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[1]   ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|datab_node[1]   ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~4             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~4             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~5             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~5             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~6             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~6             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~7             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~7             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~8             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~8             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~9             ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~9             ; out0             ;
; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~10            ; |lcnt8|lcnt:inst1|lpm_add_sub:add_rtl_0|addcore:adder|_~10            ; out0             ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------------+