lcnt8.fit.qmsg

这个是用VHDL实现的正负脉宽调制器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 31 21:23:10 2008 " "Info: Processing started: Mon Mar 31 21:23:10 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lcnt8 -c lcnt8 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcnt8 -c lcnt8" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "lcnt8 EP1C3T100C6 " "Info: Automatically selected device EP1C3T100C6 for design lcnt8" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "18 18 " "Info: No exact pin location assignment(s) for 18 pins of 18 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "psout " "Info: Pin psout not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 120 704 880 136 "psout" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "psout" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { psout } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { psout } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 16 -56 112 32 "clk" "" } { 112 144 168 128 "clk" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { clk } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[2\] " "Info: Pin b\[2\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[2\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[2] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[3\] " "Info: Pin b\[3\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[3\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[3] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[0\] " "Info: Pin b\[0\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[0\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[0] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[1\] " "Info: Pin b\[1\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[1\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[1] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[4\] " "Info: Pin b\[4\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[4\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[4] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[5\] " "Info: Pin b\[5\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[5\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[5] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[6\] " "Info: Pin b\[6\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[6\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[6] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[7\] " "Info: Pin b\[7\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "b\[7\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[7] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { b[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[2\] " "Info: Pin a\[2\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[2\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[2] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[3\] " "Info: Pin a\[3\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[3\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[3] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[0\] " "Info: Pin a\[0\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[0\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[0] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[1\] " "Info: Pin a\[1\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[1\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[1] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[4\] " "Info: Pin a\[4\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[4\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[4] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[5\] " "Info: Pin a\[5\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[5\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[5] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[6\] " "Info: Pin a\[6\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[6\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[6] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[7\] " "Info: Pin a\[7\] not assigned to an exact location on the device" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "a\[7\]" } } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[7] } "NODE_NAME" } "" } } { "E:/study/lcnt8/lcnt8.fld" "" { Floorplan "E:/study/lcnt8/lcnt8.fld" "" "" { a[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 10 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 10" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 16 -56 112 32 "clk" "" } { 112 144 168 128 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}