lcnt8.map.qmsg

这个是用VHDL实现的正负脉宽调制器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 31 21:23:07 2008 " "Info: Processing started: Mon Mar 31 21:23:07 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcnt8 -c lcnt8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcnt8 -c lcnt8" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcnt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcnt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcnt-lcnt_architecture " "Info: Found design unit 1: lcnt-lcnt_architecture" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lcnt " "Info: Found entity 1: lcnt" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcnt8.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcnt8.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcnt8 " "Info: Found entity 1: lcnt8" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcnt8 " "Info: Elaborating entity \"lcnt8\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcnt lcnt:inst " "Info: Elaborating entity \"lcnt\" for hierarchy \"lcnt:inst\"" {  } { { "lcnt8.bdf" "inst" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 104 168 280 224 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "41 " "Info: Implemented 41 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "23 " "Info: Implemented 23 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 21:23:08 2008 " "Info: Processing ended: Mon Mar 31 21:23:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}