lcnt8.tan.qmsg

这个是用VHDL实现的正负脉宽调制器

{ "Info" "ITDB_TH_RESULT" "lcnt:inst1\|count\[7\] b\[7\] clk -2.996 ns register " "Info: th for register \"lcnt:inst1\|count\[7\]\" (data pin = \"b\[7\]\", clock pin = \"clk\") is -2.996 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { clk } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 16 -56 112 32 "clk" "" } { 112 144 168 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns lcnt:inst1\|count\[7\] 2 REG LC_X11_Y10_N7 2 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'lcnt:inst1\|count\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "0.998 ns" { clk lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.81 % ) " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns ( 21.19 % ) " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.128 ns" { clk lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 lcnt:inst1|count[7] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.136 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns b\[7\] 1 PIN PIN_90 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_90; Fanout = 1; PIN Node = 'b\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { b[7] } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 328 -64 104 344 "b\[7..0\]" "" } { 144 320 376 160 "b\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.912 ns) + CELL(0.089 ns) 5.136 ns lcnt:inst1\|count\[7\] 2 REG LC_X11_Y10_N7 2 " "Info: 2: + IC(3.912 ns) + CELL(0.089 ns) = 5.136 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'lcnt:inst1\|count\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "4.001 ns" { b[7] lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns ( 23.83 % ) " "Info: Total cell delay = 1.224 ns ( 23.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.912 ns ( 76.17 % ) " "Info: Total interconnect delay = 3.912 ns ( 76.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.136 ns" { b[7] lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.136 ns" { b[7] b[7]~out0 lcnt:inst1|count[7] } { 0.000ns 0.000ns 3.912ns } { 0.000ns 1.135ns 0.089ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.128 ns" { clk lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 lcnt:inst1|count[7] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.136 ns" { b[7] lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.136 ns" { b[7] b[7]~out0 lcnt:inst1|count[7] } { 0.000ns 0.000ns 3.912ns } { 0.000ns 1.135ns 0.089ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 21:23:16 2008 " "Info: Processing ended: Mon Mar 31 21:23:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}