lcnt8.tan.qmsg

这个是用VHDL实现的正负脉宽调制器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "11 " "Warning: Found 11 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "lcnt:inst1\|cao~65 " "Info: Detected gated clock \"lcnt:inst1\|cao~65\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 36 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|cao~65" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[7\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[7\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[6\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[6\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[5\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[5\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[4\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[4\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcnt:inst1\|cao~64 " "Info: Detected gated clock \"lcnt:inst1\|cao~64\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 36 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|cao~64" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[3\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[3\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[0\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[0\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[1\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[1\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcnt:inst1\|count\[2\] " "Info: Detected ripple clock \"lcnt:inst1\|count\[2\]\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|count\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcnt:inst1\|cao~66 " "Info: Detected gated clock \"lcnt:inst1\|cao~66\" as buffer" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 36 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "lcnt:inst1\|cao~66" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register inst6 register lcnt:inst\|count\[7\] 195.47 MHz 5.116 ns Internal " "Info: Clock \"clk\" has Internal fmax of 195.47 MHz between source register \"inst6\" and destination register \"lcnt:inst\|count\[7\]\" (period= 5.116 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.917 ns + Longest register register " "Info: + Longest register to register delay is 1.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst6 1 REG LC_X11_Y10_N8 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y10_N8; Fanout = 17; REG Node = 'inst6'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { inst6 } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 104 592 656 184 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.974 ns) + CELL(0.943 ns) 1.917 ns lcnt:inst\|count\[7\] 2 REG LC_X12_Y10_N7 2 " "Info: 2: + IC(0.974 ns) + CELL(0.943 ns) = 1.917 ns; Loc. = LC_X12_Y10_N7; Fanout = 2; REG Node = 'lcnt:inst\|count\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "1.917 ns" { inst6 lcnt:inst|count[7] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.943 ns ( 49.19 % ) " "Info: Total cell delay = 0.943 ns ( 49.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.974 ns ( 50.81 % ) " "Info: Total interconnect delay = 0.974 ns ( 50.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "1.917 ns" { inst6 lcnt:inst|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "1.917 ns" { inst6 lcnt:inst|count[7] } { 0.000ns 0.974ns } { 0.000ns 0.943ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.997 ns - Smallest " "Info: - Smallest clock skew is -2.997 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { clk } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 16 -56 112 32 "clk" "" } { 112 144 168 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns lcnt:inst\|count\[7\] 2 REG LC_X12_Y10_N7 2 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X12_Y10_N7; Fanout = 2; REG Node = 'lcnt:inst\|count\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "0.998 ns" { clk lcnt:inst|count[7] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.81 % ) " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns ( 21.19 % ) " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.128 ns" { clk lcnt:inst|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 lcnt:inst|count[7] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.125 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { clk } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 16 -56 112 32 "clk" "" } { 112 144 168 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.720 ns) 2.301 ns lcnt:inst1\|count\[7\] 2 REG LC_X11_Y10_N7 2 " "Info: 2: + IC(0.451 ns) + CELL(0.720 ns) = 2.301 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'lcnt:inst1\|count\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "1.171 ns" { clk lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.454 ns) 3.172 ns lcnt:inst1\|cao~65 3 COMB LC_X11_Y10_N9 1 " "Info: 3: + IC(0.417 ns) + CELL(0.454 ns) = 3.172 ns; Loc. = LC_X11_Y10_N9; Fanout = 1; COMB Node = 'lcnt:inst1\|cao~65'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "0.871 ns" { lcnt:inst1|count[7] lcnt:inst1|cao~65 } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.340 ns) 4.025 ns lcnt:inst1\|cao~66 4 COMB LC_X10_Y10_N2 1 " "Info: 4: + IC(0.513 ns) + CELL(0.340 ns) = 4.025 ns; Loc. = LC_X10_Y10_N2; Fanout = 1; COMB Node = 'lcnt:inst1\|cao~66'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "0.853 ns" { lcnt:inst1|cao~65 lcnt:inst1|cao~66 } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.547 ns) 5.125 ns inst6 5 REG LC_X11_Y10_N8 17 " "Info: 5: + IC(0.553 ns) + CELL(0.547 ns) = 5.125 ns; Loc. = LC_X11_Y10_N8; Fanout = 17; REG Node = 'inst6'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "1.100 ns" { lcnt:inst1|cao~66 inst6 } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 104 592 656 184 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.191 ns ( 62.26 % ) " "Info: Total cell delay = 3.191 ns ( 62.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.934 ns ( 37.74 % ) " "Info: Total interconnect delay = 1.934 ns ( 37.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.125 ns" { clk lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.125 ns" { clk clk~out0 lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } { 0.000ns 0.000ns 0.451ns 0.417ns 0.513ns 0.553ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.128 ns" { clk lcnt:inst|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 lcnt:inst|count[7] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.125 ns" { clk lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.125 ns" { clk clk~out0 lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } { 0.000ns 0.000ns 0.451ns 0.417ns 0.513ns 0.553ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 104 592 656 184 "inst6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "1.917 ns" { inst6 lcnt:inst|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "1.917 ns" { inst6 lcnt:inst|count[7] } { 0.000ns 0.974ns } { 0.000ns 0.943ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.128 ns" { clk lcnt:inst|count[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 lcnt:inst|count[7] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.125 ns" { clk lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.125 ns" { clk clk~out0 lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } { 0.000ns 0.000ns 0.451ns 0.417ns 0.513ns 0.553ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.547ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lcnt:inst\|count\[0\] a\[0\] clk 4.152 ns register " "Info: tsu for register \"lcnt:inst\|count\[0\]\" (data pin = \"a\[0\]\", clock pin = \"clk\") is 4.152 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.251 ns + Longest pin register " "Info: + Longest pin to register delay is 6.251 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns a\[0\] 1 PIN PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_39; Fanout = 1; PIN Node = 'a\[0\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { a[0] } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 152 -56 112 168 "a\[7..0\]" "" } { 144 112 168 160 "a\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.027 ns) + CELL(0.089 ns) 6.251 ns lcnt:inst\|count\[0\] 2 REG LC_X12_Y10_N0 4 " "Info: 2: + IC(5.027 ns) + CELL(0.089 ns) = 6.251 ns; Loc. = LC_X12_Y10_N0; Fanout = 4; REG Node = 'lcnt:inst\|count\[0\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.116 ns" { a[0] lcnt:inst|count[0] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns ( 19.58 % ) " "Info: Total cell delay = 1.224 ns ( 19.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.027 ns ( 80.42 % ) " "Info: Total interconnect delay = 5.027 ns ( 80.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "6.251 ns" { a[0] lcnt:inst|count[0] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "6.251 ns" { a[0] a[0]~out0 lcnt:inst|count[0] } { 0.000ns 0.000ns 5.027ns } { 0.000ns 1.135ns 0.089ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { clk } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 16 -56 112 32 "clk" "" } { 112 144 168 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns lcnt:inst\|count\[0\] 2 REG LC_X12_Y10_N0 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X12_Y10_N0; Fanout = 4; REG Node = 'lcnt:inst\|count\[0\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "0.998 ns" { clk lcnt:inst|count[0] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.81 % ) " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns ( 21.19 % ) " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.128 ns" { clk lcnt:inst|count[0] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 lcnt:inst|count[0] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "6.251 ns" { a[0] lcnt:inst|count[0] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "6.251 ns" { a[0] a[0]~out0 lcnt:inst|count[0] } { 0.000ns 0.000ns 5.027ns } { 0.000ns 1.135ns 0.089ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.128 ns" { clk lcnt:inst|count[0] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 lcnt:inst|count[0] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk psout inst6 8.040 ns register " "Info: tco from clock \"clk\" to destination pin \"psout\" through register \"inst6\" is 8.040 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.125 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { clk } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 16 -56 112 32 "clk" "" } { 112 144 168 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.720 ns) 2.301 ns lcnt:inst1\|count\[7\] 2 REG LC_X11_Y10_N7 2 " "Info: 2: + IC(0.451 ns) + CELL(0.720 ns) = 2.301 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'lcnt:inst1\|count\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "1.171 ns" { clk lcnt:inst1|count[7] } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.454 ns) 3.172 ns lcnt:inst1\|cao~65 3 COMB LC_X11_Y10_N9 1 " "Info: 3: + IC(0.417 ns) + CELL(0.454 ns) = 3.172 ns; Loc. = LC_X11_Y10_N9; Fanout = 1; COMB Node = 'lcnt:inst1\|cao~65'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "0.871 ns" { lcnt:inst1|count[7] lcnt:inst1|cao~65 } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.340 ns) 4.025 ns lcnt:inst1\|cao~66 4 COMB LC_X10_Y10_N2 1 " "Info: 4: + IC(0.513 ns) + CELL(0.340 ns) = 4.025 ns; Loc. = LC_X10_Y10_N2; Fanout = 1; COMB Node = 'lcnt:inst1\|cao~66'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "0.853 ns" { lcnt:inst1|cao~65 lcnt:inst1|cao~66 } "NODE_NAME" } "" } } { "lcnt.vhd" "" { Text "E:/study/lcnt8/lcnt.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.547 ns) 5.125 ns inst6 5 REG LC_X11_Y10_N8 17 " "Info: 5: + IC(0.553 ns) + CELL(0.547 ns) = 5.125 ns; Loc. = LC_X11_Y10_N8; Fanout = 17; REG Node = 'inst6'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "1.100 ns" { lcnt:inst1|cao~66 inst6 } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 104 592 656 184 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.191 ns ( 62.26 % ) " "Info: Total cell delay = 3.191 ns ( 62.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.934 ns ( 37.74 % ) " "Info: Total interconnect delay = 1.934 ns ( 37.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.125 ns" { clk lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.125 ns" { clk clk~out0 lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } { 0.000ns 0.000ns 0.451ns 0.417ns 0.513ns 0.553ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 104 592 656 184 "inst6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.742 ns + Longest register pin " "Info: + Longest register to pin delay is 2.742 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst6 1 REG LC_X11_Y10_N8 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y10_N8; Fanout = 17; REG Node = 'inst6'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "" { inst6 } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 104 592 656 184 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.120 ns) + CELL(1.622 ns) 2.742 ns psout 2 PIN PIN_89 0 " "Info: 2: + IC(1.120 ns) + CELL(1.622 ns) = 2.742 ns; Loc. = PIN_89; Fanout = 0; PIN Node = 'psout'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.742 ns" { inst6 psout } "NODE_NAME" } "" } } { "lcnt8.bdf" "" { Schematic "E:/study/lcnt8/lcnt8.bdf" { { 120 704 880 136 "psout" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 59.15 % ) " "Info: Total cell delay = 1.622 ns ( 59.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.120 ns ( 40.85 % ) " "Info: Total interconnect delay = 1.120 ns ( 40.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.742 ns" { inst6 psout } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.742 ns" { inst6 psout } { 0.000ns 1.120ns } { 0.000ns 1.622ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "5.125 ns" { clk lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.125 ns" { clk clk~out0 lcnt:inst1|count[7] lcnt:inst1|cao~65 lcnt:inst1|cao~66 inst6 } { 0.000ns 0.000ns 0.451ns 0.417ns 0.513ns 0.553ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "lcnt8" "UNKNOWN" "V1" "E:/study/lcnt8/db/lcnt8.quartus_db" { Floorplan "E:/study/lcnt8/" "" "2.742 ns" { inst6 psout } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.742 ns" { inst6 psout } { 0.000ns 1.120ns } { 0.000ns 1.622ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}