lcnt8.fit.rpt

这个是用VHDL实现的正负脉宽调制器

+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 5.75) ; Number of LABs  (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 1                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 2                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 2.75) ; Number of LABs  (Total = 4) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 2                           ;
; 2                                               ; 0                           ;
; 3                                               ; 1                           ;
; 4                                               ; 0                           ;
; 5                                               ; 0                           ;
; 6                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 7.25) ; Number of LABs  (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 1                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 1                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 0                           ;
; 11                                          ; 2                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon Mar 31 21:23:10 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcnt8 -c lcnt8
Info: Automatically selected device EP1C3T100C6 for design lcnt8
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: No exact pin location assignment(s) for 18 pins of 18 total pins
    Info: Pin psout not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin b[2] not assigned to an exact location on the device
    Info: Pin b[3] not assigned to an exact location on the device
    Info: Pin b[0] not assigned to an exact location on the device
    Info: Pin b[1] not assigned to an exact location on the device
    Info: Pin b[4] not assigned to an exact location on the device
    Info: Pin b[5] not assigned to an exact location on the device
    Info: Pin b[6] not assigned to an exact location on the device
    Info: Pin b[7] not assigned to an exact location on the device
    Info: Pin a[2] not assigned to an exact location on the device
    Info: Pin a[3] not assigned to an exact location on the device
    Info: Pin a[0] not assigned to an exact location on the device
    Info: Pin a[1] not assigned to an exact location on the device
    Info: Pin a[4] not assigned to an exact location on the device
    Info: Pin a[5] not assigned to an exact location on the device
    Info: Pin a[6] not assigned to an exact location on the device
    Info: Pin a[7] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 17 (unused VREF, 3.30 VCCIO, 16 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 1.509 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y10; Fanout = 17; REG Node = 'inst6'
    Info: 2: + IC(0.566 ns) + CELL(0.943 ns) = 1.509 ns; Loc. = LAB_X12_Y10; Fanout = 4; REG Node = 'lcnt:inst|count[2]'
    Info: Total cell delay = 0.943 ns ( 62.49 % )
    Info: Total interconnect delay = 0.566 ns ( 37.51 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Mar 31 21:23:12 2008
    Info: Elapsed time: 00:00:03