lcnt.vhd

这个是用VHDL实现的正负脉宽调制器

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.1 (Build Build 213 01/19/2006)
-- Created on Sat Mar 29 17:27:09 2008

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY lcnt IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk : IN STD_LOGIC;
		ld : IN STD_LOGIC;
		d : IN integer range 0 to 255;
		cao : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END lcnt;


--  Architecture Body

ARCHITECTURE lcnt_architecture OF lcnt IS
signal count:integer range 0 to 255;
	
BEGIN
  process(clk)
   begin
     if rising_edge(clk) then
      if ld='1' then
         count<=d;
      else
         count<=count+1;
      end if;
     end if;
  end process;

  process(count)
   begin
     if count=255 then
        cao<='1';
     else
        cao<='0';
     end if;
  end process;  

END lcnt_architecture;