add8.fit.summary

来自「这是用VHDL实现的8位加法器」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Sat Mar 29 10:25:06 2008
Quartus II Version : 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
Revision Name : add8
Top-level Entity Name : add8
Family : Cyclone
Device : EP1C3T100C6
Timing Models : Final
Total logic elements : 10 / 2,910 ( < 1 % )
Total pins : 26 / 65 ( 40 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )