add4b.vhd

这是用VHDL实现的8位加法器

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.1 (Build Build 213 01/19/2006)
-- Created on Sat Mar 29 09:27:14 2008

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--  Entity Declaration

ENTITY add4b IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		cin : IN STD_LOGIC;
		a : IN STD_LOGIC_VECTOR(3 downto 0);
		b : IN STD_LOGIC_VECTOR(3 downto 0);
		cout : OUT STD_LOGIC;
		s : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END add4b;


--  Architecture Body

ARCHITECTURE add4b_architecture OF add4b IS

SIGNAL sint:std_logic_vector(4 downto 0);
SIGNAL aa,bb:std_logic_vector(4 downto 0);
	
BEGIN

 aa<='0'&a;
 bb<='0'&b;
 sint<=aa+bb+cin;
 s<=sint(3 downto 0);
 cout<=sint(4);

END add4b_architecture;