add8.vhd

这是用VHDL实现的8位加法器

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY add8 IS 
	port
	(
		cin :  IN  STD_LOGIC;
		a :  IN  STD_LOGIC_VECTOR(7 downto 0);
		b :  IN  STD_LOGIC_VECTOR(7 downto 0);
		cout :  OUT  STD_LOGIC;
		s :  OUT  STD_LOGIC_VECTOR(7 downto 0)
	);
END add8;

ARCHITECTURE bdf_type OF add8 IS 

component add4b
	PORT(cin : IN STD_LOGIC;
		 a : IN STD_LOGIC_VECTOR(3 downto 0);
		 b : IN STD_LOGIC_VECTOR(3 downto 0);
		 cout : OUT STD_LOGIC;
		 s : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

signal	carry_out :  STD_LOGIC;
signal	s_ALTERA_SYNTHESIZED :  STD_LOGIC_VECTOR(7 downto 0);


BEGIN 



b2v_inst : add4b
PORT MAP(cin => cin,
		 a => a(3 downto 0),
		 b => b(3 downto 0),
		 cout => carry_out,
		 s => s_ALTERA_SYNTHESIZED(3 downto 0));

b2v_inst5 : add4b
PORT MAP(cin => carry_out,
		 a => a(7 downto 4),
		 b => b(7 downto 4),
		 cout => cout,
		 s => s_ALTERA_SYNTHESIZED(7 downto 4));
s <= s_ALTERA_SYNTHESIZED;

END;