add8.map.summary

来自「这是用VHDL实现的8位加法器」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sat Mar 29 10:25:03 2008
Quartus II Version : 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
Revision Name : add8
Top-level Entity Name : add8
Family : Cyclone
Total logic elements : 10
Total pins : 26
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0