trans.vhd

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TRANS IS
	PORT(CLK:IN STD_LOGIC;
		 OUTDATAENIN:IN STD_LOGIC;
		 IOUTIN:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		 QOUTIN:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		 IOUTOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 QOUTOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 ADDRIN:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		 ADDROUT:OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
		OUTDATAENOUT:OUT STD_LOGIC;
		RDCLK:OUT STD_LOGIC;
		WRCLK:OUT STD_LOGIC
		);
END TRANS;
ARCHITECTURE ART OF TRANS IS
BEGIN
	ADDROUT<=ADDRIN;
	IOUTOUT<=IOUTIN(9 DOWNTO 2);
	QOUTOUT<=QOUTIN(9 DOWNTO 2);
	RDCLK<=CLK;
	WRCLK<=NOT CLK;
	OUTDATAENOUT<=OUTDATAENIN;
END ART;