ffti.hier_info

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

clk => RegAI[0][5].CLK
clk => RegAI[0][4].CLK
clk => RegAI[0][3].CLK
clk => RegAI[0][2].CLK
clk => RegAI[0][1].CLK
clk => RegAI[0][0].CLK
clk => RegAQ[3][7].CLK
clk => RegAQ[3][6].CLK
clk => RegAQ[3][5].CLK
clk => RegAQ[3][4].CLK
clk => RegAQ[3][3].CLK
clk => RegAQ[3][2].CLK
clk => RegAQ[3][1].CLK
clk => RegAQ[3][0].CLK
clk => RegAQ[2][7].CLK
clk => RegAQ[2][6].CLK
clk => RegAQ[2][5].CLK
clk => RegAQ[2][4].CLK
clk => RegAQ[2][3].CLK
clk => RegAQ[2][2].CLK
clk => RegAQ[2][1].CLK
clk => RegAQ[2][0].CLK
clk => RegAQ[1][7].CLK
clk => RegAQ[1][6].CLK
clk => RegAQ[1][5].CLK
clk => RegAQ[1][4].CLK
clk => RegAQ[1][3].CLK
clk => RegAQ[1][2].CLK
clk => RegAQ[1][1].CLK
clk => RegAQ[1][0].CLK
clk => RegAQ[0][7].CLK
clk => RegAQ[0][6].CLK
clk => RegAQ[0][5].CLK
clk => RegAQ[0][4].CLK
clk => RegAQ[0][3].CLK
clk => RegAQ[0][2].CLK
clk => RegAQ[0][1].CLK
clk => RegAQ[0][0].CLK
clk => RegBI[3][8].CLK
clk => RegBI[3][7].CLK
clk => RegBI[3][6].CLK
clk => RegBI[3][5].CLK
clk => RegBI[3][4].CLK
clk => RegBI[3][3].CLK
clk => RegBI[3][2].CLK
clk => RegBI[3][1].CLK
clk => RegBI[3][0].CLK
clk => RegBI[2][8].CLK
clk => RegBI[2][7].CLK
clk => RegBI[2][6].CLK
clk => RegBI[2][5].CLK
clk => RegBI[2][4].CLK
clk => RegBI[2][3].CLK
clk => RegBI[2][2].CLK
clk => RegBI[2][1].CLK
clk => RegBI[2][0].CLK
clk => RegBI[1][8].CLK
clk => RegBI[1][7].CLK
clk => RegBI[1][6].CLK
clk => RegBI[1][5].CLK
clk => RegBI[1][4].CLK
clk => RegBI[1][3].CLK
clk => RegBI[1][2].CLK
clk => RegBI[1][1].CLK
clk => RegBI[1][0].CLK
clk => RegBI[0][8].CLK
clk => RegBI[0][7].CLK
clk => RegBI[0][6].CLK
clk => RegBI[0][5].CLK
clk => RegBI[0][4].CLK
clk => RegBI[0][3].CLK
clk => RegBI[0][2].CLK
clk => RegBI[0][1].CLK
clk => RegBI[0][0].CLK
clk => RegBQ[3][8].CLK
clk => RegBQ[3][7].CLK
clk => RegBQ[3][6].CLK
clk => RegBQ[3][5].CLK
clk => RegBQ[3][4].CLK
clk => RegBQ[3][3].CLK
clk => RegBQ[3][2].CLK
clk => RegBQ[3][1].CLK
clk => RegBQ[3][0].CLK
clk => RegBQ[2][8].CLK
clk => RegBQ[2][7].CLK
clk => RegBQ[2][6].CLK
clk => RegBQ[2][5].CLK
clk => RegBQ[2][4].CLK
clk => RegBQ[2][3].CLK
clk => RegBQ[2][2].CLK
clk => RegBQ[2][1].CLK
clk => RegBQ[2][0].CLK
clk => RegBQ[1][8].CLK
clk => RegBQ[1][7].CLK
clk => RegBQ[1][6].CLK
clk => RegBQ[1][5].CLK
clk => RegBQ[1][4].CLK
clk => RegBQ[1][3].CLK
clk => RegBQ[1][2].CLK
clk => RegBQ[1][1].CLK
clk => RegBQ[1][0].CLK
clk => RegBQ[0][8].CLK
clk => RegBQ[0][7].CLK
clk => RegBQ[0][6].CLK
clk => RegBQ[0][5].CLK
clk => RegBQ[0][4].CLK
clk => RegBQ[0][3].CLK
clk => RegBQ[0][2].CLK
clk => RegBQ[0][1].CLK
clk => RegBQ[0][0].CLK
clk => Iout[9]~reg0.CLK
clk => Iout[8]~reg0.CLK
clk => Iout[7]~reg0.CLK
clk => Iout[6]~reg0.CLK
clk => Iout[5]~reg0.CLK
clk => Iout[4]~reg0.CLK
clk => Iout[3]~reg0.CLK
clk => Iout[2]~reg0.CLK
clk => Iout[1]~reg0.CLK
clk => Iout[0]~reg0.CLK
clk => Qout[9]~reg0.CLK
clk => Qout[8]~reg0.CLK
clk => Qout[7]~reg0.CLK
clk => Qout[6]~reg0.CLK
clk => Qout[5]~reg0.CLK
clk => Qout[4]~reg0.CLK
clk => Qout[3]~reg0.CLK
clk => Qout[2]~reg0.CLK
clk => Qout[1]~reg0.CLK
clk => Qout[0]~reg0.CLK
rst => counter[1].ACLR
rst => counter[0].ACLR
start => counter~1.OUTPUTSELECT
start => counter~0.OUTPUTSELECT
invert => RegBQ~8.OUTPUTSELECT
invert => RegBQ~7.OUTPUTSELECT
invert => RegBQ~6.OUTPUTSELECT
invert => RegBQ~5.OUTPUTSELECT
invert => RegBQ~4.OUTPUTSELECT
invert => RegBQ~3.OUTPUTSELECT
invert => RegBQ~2.OUTPUTSELECT
invert => RegBQ~1.OUTPUTSELECT
invert => RegBQ~0.OUTPUTSELECT
invert => RegBI~8.OUTPUTSELECT
invert => RegBI~7.OUTPUTSELECT
invert => RegBI~6.OUTPUTSELECT
invert => RegBI~5.OUTPUTSELECT
invert => RegBI~4.OUTPUTSELECT
invert => RegBI~3.OUTPUTSELECT
invert => RegBI~2.OUTPUTSELECT
invert => RegBI~1.OUTPUTSELECT
invert => RegBI~0.OUTPUTSELECT
I[0] => Mux31.IN0
I[0] => Mux23.IN0
I[0] => Mux15.IN0
I[0] => Mux7.IN0
I[1] => Mux30.IN0
I[1] => Mux22.IN0
I[1] => Mux14.IN0
I[1] => Mux6.IN0
I[2] => Mux29.IN0
I[2] => Mux21.IN0
I[2] => Mux13.IN0
I[2] => Mux5.IN0
I[3] => Mux28.IN0
I[3] => Mux20.IN0
I[3] => Mux12.IN0
I[3] => Mux4.IN0
I[4] => Mux27.IN0
I[4] => Mux19.IN0
I[4] => Mux11.IN0
I[4] => Mux3.IN0
I[5] => Mux26.IN0
I[5] => Mux18.IN0
I[5] => Mux10.IN0
I[5] => Mux2.IN0
I[6] => Mux25.IN0
I[6] => Mux17.IN0
I[6] => Mux9.IN0
I[6] => Mux1.IN0
I[7] => Mux24.IN0
I[7] => Mux16.IN0
I[7] => Mux8.IN0
I[7] => Mux0.IN0
Q[0] => Mux63.IN0
Q[0] => Mux55.IN0
Q[0] => Mux47.IN0
Q[0] => Mux39.IN0
Q[1] => Mux62.IN0
Q[1] => Mux54.IN0
Q[1] => Mux46.IN0
Q[1] => Mux38.IN0
Q[2] => Mux61.IN0
Q[2] => Mux53.IN0
Q[2] => Mux45.IN0
Q[2] => Mux37.IN0
Q[3] => Mux60.IN0
Q[3] => Mux52.IN0
Q[3] => Mux44.IN0
Q[3] => Mux36.IN0
Q[4] => Mux59.IN0
Q[4] => Mux51.IN0
Q[4] => Mux43.IN0
Q[4] => Mux35.IN0
Q[5] => Mux58.IN0
Q[5] => Mux50.IN0
Q[5] => Mux42.IN0
Q[5] => Mux34.IN0
Q[6] => Mux57.IN0
Q[6] => Mux49.IN0
Q[6] => Mux41.IN0
Q[6] => Mux33.IN0
Q[7] => Mux56.IN0
Q[7] => Mux48.IN0
Q[7] => Mux40.IN0
Q[7] => Mux32.IN0
Iout[0] <= Iout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[1] <= Iout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[2] <= Iout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[3] <= Iout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[4] <= Iout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[5] <= Iout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[6] <= Iout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[7] <= Iout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[8] <= Iout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Iout[9] <= Iout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[0] <= Qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[1] <= Qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[2] <= Qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[3] <= Qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[4] <= Qout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[5] <= Qout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[6] <= Qout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[7] <= Qout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[8] <= Qout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Qout[9] <= Qout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ffti|cfft1024X12:inst1|cfft:aCfft|div4limit:Ilimit
clk => Q[7]~reg0.CLK
clk => Q[6]~reg0.CLK
clk => Q[5]~reg0.CLK
clk => Q[4]~reg0.CLK
clk => Q[3]~reg0.CLK
clk => Q[2]~reg0.CLK
clk => Q[1]~reg0.CLK
clk => Q[0]~reg0.CLK
D[0] => ~NO_FANOUT~
D[1] => Add0.IN20
D[2] => Add0.IN19
D[3] => Add0.IN18
D[4] => Add0.IN17
D[5] => Add0.IN16
D[6] => Add0.IN15
D[7] => Add0.IN14
D[8] => Add0.IN13
D[9] => Add0.IN12
D[10] => Add0.IN11
D[11] => Add0.IN10
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ffti|cfft1024X12:inst1|cfft:aCfft|div4limit:Qlimit
clk => Q[7]~reg0.CLK
clk => Q[6]~reg0.CLK
clk => Q[5]~reg0.CLK
clk => Q[4]~reg0.CLK
clk => Q[3]~reg0.CLK
clk => Q[2]~reg0.CLK
clk => Q[1]~reg0.CLK
clk => Q[0]~reg0.CLK
D[0] => ~NO_FANOUT~
D[1] => Add0.IN20
D[2] => Add0.IN19
D[3] => Add0.IN18
D[4] => Add0.IN17
D[5] => Add0.IN16
D[6] => Add0.IN15
D[7] => Add0.IN14
D[8] => Add0.IN13
D[9] => Add0.IN12
D[10] => Add0.IN11
D[11] => Add0.IN10
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ffti|cfft1024X12:inst1|cfft:aCfft|mulfactor:amulfactor
clk => phase[7].CLK
clk => phase[6].CLK
clk => phase[5].CLK
clk => phase[4].CLK
clk => phase[3].CLK
clk => phase[2].CLK
clk => phase[1].CLK
clk => phase[0].CLK
clk => Xi[9].CLK
clk => Xi[8].CLK
clk => Xi[7].CLK
clk => Xi[6].CLK
clk => Xi[5].CLK
clk => Xi[4].CLK
clk => Xi[3].CLK
clk => Xi[2].CLK
clk => Xi[1].CLK
clk => Xi[0].CLK
clk => Yi[9].CLK
clk => Yi[8].CLK
clk => Yi[7].CLK
clk => Yi[6].CLK
clk => Yi[5].CLK
clk => Yi[4].CLK
clk => Yi[3].CLK
clk => Yi[2].CLK
clk => Yi[1].CLK
clk => Yi[0].CLK
clk => sc_corproc:u1.clk
rst => phase[7].ACLR
rst => phase[6].ACLR
rst => phase[5].ACLR
rst => phase[4].ACLR
rst => phase[3].ACLR
rst => phase[2].ACLR
rst => phase[1].ACLR
rst => phase[0].ACLR
rst => Xi[9].ACLR
rst => Xi[8].ACLR
rst => Xi[7].ACLR
rst => Xi[6].ACLR
rst => Xi[5].ACLR
rst => Xi[4].ACLR
rst => Xi[3].ACLR
rst => Xi[2].ACLR
rst => Xi[1].ACLR
rst => Xi[0].ACLR
rst => Yi[9].ACLR
rst => Yi[8].ACLR
rst => Yi[7].ACLR
rst => Yi[6].ACLR
rst => Yi[5].ACLR
rst => Yi[4].ACLR
rst => Yi[3].ACLR
rst => Yi[2].ACLR
rst => Yi[1].ACLR
rst => Yi[0].ACLR
angle[0] => phase[0].DATAIN
angle[1] => phase[1].DATAIN
angle[2] => phase[2].DATAIN
angle[3] => phase[3].DATAIN
angle[4] => phase[4].DATAIN
angle[5] => phase[5].DATAIN
angle[6] => phase[6].DATAIN
angle[7] => phase[7].DATAIN
angle[8] => Mux19.IN3
angle[8] => Mux18.IN3
angle[8] => Mux17.IN3
angle[8] => Mux16.IN3
angle[8] => Mux15.IN3
angle[8] => Mux14.IN3
angle[8] => Mux13.IN3
angle[8] => Mux12.IN3
angle[8] => Mux11.IN3
angle[8] => Mux10.IN3
angle[8] => Mux9.IN3
angle[8] => Mux8.IN3
angle[8] => Mux7.IN3
angle[8] => Mux6.IN3
angle[8] => Mux5.IN3
angle[8] => Mux4.IN3
angle[8] => Mux3.IN3
angle[8] => Mux2.IN3
angle[8] => Mux1.IN3
angle[8] => Mux0.IN3
angle[9] => Mux19.IN2
angle[9] => Mux18.IN2
angle[9] => Mux17.IN2
angle[9] => Mux16.IN2
angle[9] => Mux15.IN2
angle[9] => Mux14.IN2
angle[9] => Mux13.IN2
angle[9] => Mux12.IN2
angle[9] => Mux11.IN2
angle[9] => Mux10.IN2
angle[9] => Mux9.IN2
angle[9] => Mux8.IN2
angle[9] => Mux7.IN2
angle[9] => Mux6.IN2
angle[9] => Mux5.IN2
angle[9] => Mux4.IN2
angle[9] => Mux3.IN2
angle[9] => Mux2.IN2
angle[9] => Mux1.IN2
angle[9] => Mux0.IN2
I[0] => Mux19.IN4
I[0] => Mux9.IN4
I[0] => Add1.IN0
I[1] => Mux18.IN4
I[1] => Mux8.IN4
I[1] => Add1.IN1
I[2] => Mux17.IN4
I[2] => Mux7.IN4
I[2] => Add1.IN2
I[3] => Mux16.IN4
I[3] => Mux6.IN4
I[3] => Add1.IN3
I[4] => Mux15.IN4
I[4] => Mux5.IN4
I[4] => Add1.IN4
I[5] => Mux14.IN4
I[5] => Mux4.IN4
I[5] => Add1.IN5
I[6] => Mux13.IN4
I[6] => Mux3.IN4
I[6] => Add1.IN6
I[7] => Mux12.IN4
I[7] => Mux2.IN4
I[7] => Add1.IN7
I[8] => Mux11.IN4
I[8] => Mux1.IN4
I[8] => Add1.IN8
I[9] => Mux10.IN4
I[9] => Mux0.IN4
I[9] => Add1.IN9
Q[0] => Mux19.IN5
Q[0] => Mux9.IN5
Q[0] => Add0.IN0
Q[1] => Mux18.IN5
Q[1] => Mux8.IN5
Q[1] => Add0.IN1
Q[2] => Mux17.IN5
Q[2] => Mux7.IN5
Q[2] => Add0.IN2
Q[3] => Mux16.IN5
Q[3] => Mux6.IN5
Q[3] => Add0.IN3
Q[4] => Mux15.IN5
Q[4] => Mux5.IN5
Q[4] => Add0.IN4
Q[5] => Mux14.IN5
Q[5] => Mux4.IN5
Q[5] => Add0.IN5
Q[6] => Mux13.IN5
Q[6] => Mux3.IN5
Q[6] => Add0.IN6
Q[7] => Mux12.IN5
Q[7] => Mux2.IN5
Q[7] => Add0.IN7
Q[8] => Mux11.IN5
Q[8] => Mux1.IN5