ffti.hier_info

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

clk => outcounter[6].CLK
clk => outcounter[5].CLK
clk => outcounter[4].CLK
clk => outcounter[3].CLK
clk => outcounter[2].CLK
clk => outcounter[1].CLK
clk => outcounter[0].CLK
clk => inputbusy~reg0.CLK
clk => wdataI[7]~reg0.CLK
clk => wdataI[6]~reg0.CLK
clk => wdataI[5]~reg0.CLK
clk => wdataI[4]~reg0.CLK
clk => wdataI[3]~reg0.CLK
clk => wdataI[2]~reg0.CLK
clk => wdataI[1]~reg0.CLK
clk => wdataI[0]~reg0.CLK
clk => wdataQ[7]~reg0.CLK
clk => wdataQ[6]~reg0.CLK
clk => wdataQ[5]~reg0.CLK
clk => wdataQ[4]~reg0.CLK
clk => wdataQ[3]~reg0.CLK
clk => wdataQ[2]~reg0.CLK
clk => wdataQ[1]~reg0.CLK
clk => wdataQ[0]~reg0.CLK
rst => counter[9].ACLR
rst => counter[8].ACLR
rst => counter[7].ACLR
rst => counter[6].ACLR
rst => counter[5].ACLR
rst => counter[4].ACLR
rst => counter[3].ACLR
rst => counter[2].ACLR
rst => counter[1].ACLR
rst => counter[0].ACLR
rst => state[3].ACLR
rst => state[2].PRESET
rst => state[1].PRESET
rst => state[0].ACLR
rst => raddr[9]~reg0.ACLR
rst => raddr[8]~reg0.ACLR
rst => raddr[7]~reg0.ACLR
rst => raddr[6]~reg0.ACLR
rst => raddr[5]~reg0.ACLR
rst => raddr[4]~reg0.ACLR
rst => raddr[3]~reg0.ACLR
rst => raddr[2]~reg0.ACLR
rst => raddr[1]~reg0.ACLR
rst => raddr[0]~reg0.ACLR
rst => rcounter[9].ACLR
rst => rcounter[8].ACLR
rst => rcounter[7].ACLR
rst => rcounter[6].ACLR
rst => rcounter[5].ACLR
rst => rcounter[4].ACLR
rst => rcounter[3].ACLR
rst => rcounter[2].ACLR
rst => rcounter[1].ACLR
rst => rcounter[0].ACLR
rst => rstate[3].ACLR
rst => rstate[2].ACLR
rst => rstate[1].ACLR
rst => rstate[0].ACLR
rst => rmask1[4].ACLR
rst => rmask1[3].ACLR
rst => rmask1[2].ACLR
rst => rmask1[1].ACLR
rst => rmask1[0].ACLR
rst => rmask2[4].ACLR
rst => rmask2[3].ACLR
rst => rmask2[2].ACLR
rst => rmask2[1].ACLR
rst => rmask2[0].ACLR
rst => waddr[9]~reg0.ACLR
rst => waddr[8]~reg0.ACLR
rst => waddr[7]~reg0.ACLR
rst => waddr[6]~reg0.ACLR
rst => waddr[5]~reg0.ACLR
rst => waddr[4]~reg0.ACLR
rst => waddr[3]~reg0.ACLR
rst => waddr[2]~reg0.ACLR
rst => waddr[1]~reg0.ACLR
rst => waddr[0]~reg0.ACLR
rst => wcounter[9].ACLR
rst => wcounter[8].ACLR
rst => wcounter[7].ACLR
rst => wcounter[6].ACLR
rst => wcounter[5].ACLR
rst => wcounter[4].ACLR
rst => wcounter[3].ACLR
rst => wcounter[2].ACLR
rst => wcounter[1].ACLR
rst => wcounter[0].ACLR
rst => wmask1[4].ACLR
rst => wmask1[3].ACLR
rst => wmask1[2].ACLR
rst => wmask1[1].ACLR
rst => wmask1[0].ACLR
rst => wmask2[4].ACLR
rst => wmask2[3].ACLR
rst => wmask2[2].ACLR
rst => wmask2[1].ACLR
rst => wmask2[0].ACLR
rst => wen~reg0.ACLR
rst => factorstart~reg0.ACLR
rst => cfft4start~reg0.ACLR
rst => outcounter[10].ACLR
rst => outcounter[9].ACLR
rst => outcounter[8].ACLR
rst => outcounter[7].ACLR
rst => outcounter[6].ACLR
rst => outcounter[5].ACLR
rst => outcounter[4].ACLR
rst => outcounter[3].ACLR
rst => outcounter[2].ACLR
rst => outcounter[1].ACLR
rst => outcounter[0].ACLR
rst => inputbusy~reg0.ACLR
rst => wdataI[7]~reg0.ACLR
rst => wdataI[6]~reg0.ACLR
rst => wdataI[5]~reg0.ACLR
rst => wdataI[4]~reg0.ACLR
rst => wdataI[3]~reg0.ACLR
rst => wdataI[2]~reg0.ACLR
rst => wdataI[1]~reg0.ACLR
rst => wdataI[0]~reg0.ACLR
rst => wdataQ[7]~reg0.ACLR
rst => wdataQ[6]~reg0.ACLR
rst => wdataQ[5]~reg0.ACLR
rst => wdataQ[4]~reg0.ACLR
rst => wdataQ[3]~reg0.ACLR
rst => wdataQ[2]~reg0.ACLR
rst => wdataQ[1]~reg0.ACLR
rst => wdataQ[0]~reg0.ACLR
start => inputbusy~1.OUTPUTSELECT
start => state~11.OUTPUTSELECT
start => state~10.OUTPUTSELECT
start => state~9.OUTPUTSELECT
start => state~8.OUTPUTSELECT
start => counter~19.OUTPUTSELECT
start => counter~18.OUTPUTSELECT
start => counter~17.OUTPUTSELECT
start => counter~16.OUTPUTSELECT
start => counter~15.OUTPUTSELECT
start => counter~14.OUTPUTSELECT
start => counter~13.OUTPUTSELECT
start => counter~12.OUTPUTSELECT
start => counter~11.OUTPUTSELECT
start => counter~10.OUTPUTSELECT
Iin[0] => wdataI~7.DATAB
Iin[1] => wdataI~6.DATAB
Iin[2] => wdataI~5.DATAB
Iin[3] => wdataI~4.DATAB
Iin[4] => wdataI~3.DATAB
Iin[5] => wdataI~2.DATAB
Iin[6] => wdataI~1.DATAB
Iin[7] => wdataI~0.DATAB
Qin[0] => wdataQ~7.DATAB
Qin[1] => wdataQ~6.DATAB
Qin[2] => wdataQ~5.DATAB
Qin[3] => wdataQ~4.DATAB
Qin[4] => wdataQ~3.DATAB
Qin[5] => wdataQ~2.DATAB
Qin[6] => wdataQ~1.DATAB
Qin[7] => wdataQ~0.DATAB
fftI[0] => wdataI~7.DATAA
fftI[1] => wdataI~6.DATAA
fftI[2] => wdataI~5.DATAA
fftI[3] => wdataI~4.DATAA
fftI[4] => wdataI~3.DATAA
fftI[5] => wdataI~2.DATAA
fftI[6] => wdataI~1.DATAA
fftI[7] => wdataI~0.DATAA
fftQ[0] => wdataQ~7.DATAA
fftQ[1] => wdataQ~6.DATAA
fftQ[2] => wdataQ~5.DATAA
fftQ[3] => wdataQ~4.DATAA
fftQ[4] => wdataQ~3.DATAA
fftQ[5] => wdataQ~2.DATAA
fftQ[6] => wdataQ~1.DATAA
fftQ[7] => wdataQ~0.DATAA
wdataI[0] <= wdataI[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataI[1] <= wdataI[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataI[2] <= wdataI[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataI[3] <= wdataI[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataI[4] <= wdataI[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataI[5] <= wdataI[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataI[6] <= wdataI[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataI[7] <= wdataI[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[0] <= wdataQ[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[1] <= wdataQ[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[2] <= wdataQ[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[3] <= wdataQ[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[4] <= wdataQ[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[5] <= wdataQ[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[6] <= wdataQ[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wdataQ[7] <= wdataQ[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[0] <= raddr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[1] <= raddr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[2] <= raddr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[3] <= raddr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[4] <= raddr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[5] <= raddr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[6] <= raddr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[7] <= raddr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[8] <= raddr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
raddr[9] <= raddr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[0] <= waddr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[1] <= waddr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[2] <= waddr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[3] <= waddr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[4] <= waddr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[5] <= waddr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[6] <= waddr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[7] <= waddr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[8] <= waddr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
waddr[9] <= waddr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wen <= wen~reg0.DB_MAX_OUTPUT_PORT_TYPE
factorstart <= factorstart~reg0.DB_MAX_OUTPUT_PORT_TYPE
cfft4start <= cfft4start~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdataen <= outcounter[10].DB_MAX_OUTPUT_PORT_TYPE
inputbusy <= inputbusy~reg0.DB_MAX_OUTPUT_PORT_TYPE
OutPosition[0] <= outcounter[8].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[1] <= outcounter[9].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[2] <= outcounter[6].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[3] <= outcounter[7].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[4] <= outcounter[4].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[5] <= outcounter[5].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[6] <= outcounter[2].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[7] <= outcounter[3].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[8] <= outcounter[0].DB_MAX_OUTPUT_PORT_TYPE
OutPosition[9] <= outcounter[1].DB_MAX_OUTPUT_PORT_TYPE


|ffti|cfft1024X12:inst1|cfft:aCfft|blockdram:Iram
addra[0] => mem~9.DATAIN
addra[0] => mem.WADDR
addra[1] => mem~8.DATAIN
addra[1] => mem.WADDR1
addra[2] => mem~7.DATAIN
addra[2] => mem.WADDR2
addra[3] => mem~6.DATAIN
addra[3] => mem.WADDR3
addra[4] => mem~5.DATAIN
addra[4] => mem.WADDR4
addra[5] => mem~4.DATAIN
addra[5] => mem.WADDR5
addra[6] => mem~3.DATAIN
addra[6] => mem.WADDR6
addra[7] => mem~2.DATAIN
addra[7] => mem.WADDR7
addra[8] => mem~1.DATAIN
addra[8] => mem.WADDR8
addra[9] => mem~0.DATAIN
addra[9] => mem.WADDR9
clka => mem~17.CLK
clka => mem~16.CLK
clka => mem~15.CLK
clka => mem~14.CLK
clka => mem~13.CLK
clka => mem~12.CLK
clka => mem~11.CLK
clka => mem~10.CLK
clka => mem~9.CLK
clka => mem~8.CLK
clka => mem~7.CLK
clka => mem~6.CLK
clka => mem~5.CLK
clka => mem~4.CLK
clka => mem~3.CLK
clka => mem~2.CLK
clka => mem~1.CLK
clka => mem~0.CLK
clka => mem~18.CLK
clka => mem.CLK0
addrb[0] => addrb_reg[0].DATAIN
addrb[0] => mem.RADDR
addrb[1] => addrb_reg[1].DATAIN
addrb[1] => mem.RADDR1
addrb[2] => addrb_reg[2].DATAIN
addrb[2] => mem.RADDR2
addrb[3] => addrb_reg[3].DATAIN
addrb[3] => mem.RADDR3
addrb[4] => addrb_reg[4].DATAIN
addrb[4] => mem.RADDR4
addrb[5] => addrb_reg[5].DATAIN
addrb[5] => mem.RADDR5
addrb[6] => addrb_reg[6].DATAIN
addrb[6] => mem.RADDR6
addrb[7] => addrb_reg[7].DATAIN
addrb[7] => mem.RADDR7
addrb[8] => addrb_reg[8].DATAIN
addrb[8] => mem.RADDR8
addrb[9] => addrb_reg[9].DATAIN
addrb[9] => mem.RADDR9
clkb => addrb_reg[9].CLK
clkb => addrb_reg[8].CLK
clkb => addrb_reg[7].CLK
clkb => addrb_reg[6].CLK
clkb => addrb_reg[5].CLK
clkb => addrb_reg[4].CLK
clkb => addrb_reg[3].CLK
clkb => addrb_reg[2].CLK
clkb => addrb_reg[1].CLK
clkb => addrb_reg[0].CLK
clkb => mem.CLK1
dia[0] => mem~17.DATAIN
dia[0] => mem.DATAIN
dia[1] => mem~16.DATAIN
dia[1] => mem.DATAIN1
dia[2] => mem~15.DATAIN
dia[2] => mem.DATAIN2
dia[3] => mem~14.DATAIN
dia[3] => mem.DATAIN3
dia[4] => mem~13.DATAIN
dia[4] => mem.DATAIN4
dia[5] => mem~12.DATAIN
dia[5] => mem.DATAIN5
dia[6] => mem~11.DATAIN
dia[6] => mem.DATAIN6
dia[7] => mem~10.DATAIN
dia[7] => mem.DATAIN7
wea => mem~18.DATAIN
wea => mem.WE
dob[0] <= mem.DATAOUT
dob[1] <= mem.DATAOUT1
dob[2] <= mem.DATAOUT2
dob[3] <= mem.DATAOUT3
dob[4] <= mem.DATAOUT4
dob[5] <= mem.DATAOUT5
dob[6] <= mem.DATAOUT6
dob[7] <= mem.DATAOUT7


|ffti|cfft1024X12:inst1|cfft:aCfft|blockdram:Qram
addra[0] => mem~9.DATAIN
addra[0] => mem.WADDR
addra[1] => mem~8.DATAIN
addra[1] => mem.WADDR1
addra[2] => mem~7.DATAIN
addra[2] => mem.WADDR2
addra[3] => mem~6.DATAIN
addra[3] => mem.WADDR3
addra[4] => mem~5.DATAIN
addra[4] => mem.WADDR4
addra[5] => mem~4.DATAIN
addra[5] => mem.WADDR5
addra[6] => mem~3.DATAIN
addra[6] => mem.WADDR6
addra[7] => mem~2.DATAIN
addra[7] => mem.WADDR7
addra[8] => mem~1.DATAIN
addra[8] => mem.WADDR8
addra[9] => mem~0.DATAIN
addra[9] => mem.WADDR9
clka => mem~17.CLK
clka => mem~16.CLK
clka => mem~15.CLK
clka => mem~14.CLK
clka => mem~13.CLK
clka => mem~12.CLK
clka => mem~11.CLK
clka => mem~10.CLK
clka => mem~9.CLK
clka => mem~8.CLK
clka => mem~7.CLK
clka => mem~6.CLK
clka => mem~5.CLK
clka => mem~4.CLK
clka => mem~3.CLK
clka => mem~2.CLK
clka => mem~1.CLK
clka => mem~0.CLK
clka => mem~18.CLK
clka => mem.CLK0
addrb[0] => addrb_reg[0].DATAIN
addrb[0] => mem.RADDR
addrb[1] => addrb_reg[1].DATAIN
addrb[1] => mem.RADDR1
addrb[2] => addrb_reg[2].DATAIN
addrb[2] => mem.RADDR2
addrb[3] => addrb_reg[3].DATAIN
addrb[3] => mem.RADDR3
addrb[4] => addrb_reg[4].DATAIN
addrb[4] => mem.RADDR4
addrb[5] => addrb_reg[5].DATAIN
addrb[5] => mem.RADDR5
addrb[6] => addrb_reg[6].DATAIN
addrb[6] => mem.RADDR6
addrb[7] => addrb_reg[7].DATAIN
addrb[7] => mem.RADDR7
addrb[8] => addrb_reg[8].DATAIN
addrb[8] => mem.RADDR8
addrb[9] => addrb_reg[9].DATAIN
addrb[9] => mem.RADDR9
clkb => addrb_reg[9].CLK
clkb => addrb_reg[8].CLK
clkb => addrb_reg[7].CLK
clkb => addrb_reg[6].CLK
clkb => addrb_reg[5].CLK
clkb => addrb_reg[4].CLK
clkb => addrb_reg[3].CLK
clkb => addrb_reg[2].CLK
clkb => addrb_reg[1].CLK
clkb => addrb_reg[0].CLK
clkb => mem.CLK1
dia[0] => mem~17.DATAIN
dia[0] => mem.DATAIN
dia[1] => mem~16.DATAIN
dia[1] => mem.DATAIN1
dia[2] => mem~15.DATAIN
dia[2] => mem.DATAIN2
dia[3] => mem~14.DATAIN
dia[3] => mem.DATAIN3
dia[4] => mem~13.DATAIN
dia[4] => mem.DATAIN4
dia[5] => mem~12.DATAIN
dia[5] => mem.DATAIN5
dia[6] => mem~11.DATAIN
dia[6] => mem.DATAIN6
dia[7] => mem~10.DATAIN
dia[7] => mem.DATAIN7
wea => mem~18.DATAIN
wea => mem.WE
dob[0] <= mem.DATAOUT
dob[1] <= mem.DATAOUT1
dob[2] <= mem.DATAOUT2
dob[3] <= mem.DATAOUT3
dob[4] <= mem.DATAOUT4
dob[5] <= mem.DATAOUT5
dob[6] <= mem.DATAOUT6
dob[7] <= mem.DATAOUT7


|ffti|cfft1024X12:inst1|cfft:aCfft|cfft4:acfft4
clk => counter[1].CLK
clk => counter[0].CLK
clk => RegAI[3][7].CLK
clk => RegAI[3][6].CLK
clk => RegAI[3][5].CLK
clk => RegAI[3][4].CLK
clk => RegAI[3][3].CLK
clk => RegAI[3][2].CLK
clk => RegAI[3][1].CLK
clk => RegAI[3][0].CLK
clk => RegAI[2][7].CLK
clk => RegAI[2][6].CLK
clk => RegAI[2][5].CLK
clk => RegAI[2][4].CLK
clk => RegAI[2][3].CLK
clk => RegAI[2][2].CLK
clk => RegAI[2][1].CLK
clk => RegAI[2][0].CLK
clk => RegAI[1][7].CLK
clk => RegAI[1][6].CLK
clk => RegAI[1][5].CLK
clk => RegAI[1][4].CLK
clk => RegAI[1][3].CLK
clk => RegAI[1][2].CLK
clk => RegAI[1][1].CLK
clk => RegAI[1][0].CLK
clk => RegAI[0][7].CLK
clk => RegAI[0][6].CLK