ffti.hier_info

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

|ffti
p0[0] <= MCUBUS:inst.P0[0]
p0[1] <= MCUBUS:inst.P0[1]
p0[2] <= MCUBUS:inst.P0[2]
p0[3] <= MCUBUS:inst.P0[3]
p0[4] <= MCUBUS:inst.P0[4]
p0[5] <= MCUBUS:inst.P0[5]
p0[6] <= MCUBUS:inst.P0[6]
p0[7] <= MCUBUS:inst.P0[7]
ale => MCUBUS:inst.ALE
rd => MCUBUS:inst.RD
wr => MCUBUS:inst.WR
clk => MCUBUS:inst.CLK
clk => GEN:inst4.CLK
clk => cfft1024X12:inst1.clk
clk => ff:inst8.clock
clk => ramdata:inst10.clock
clk => TRANS:inst5.CLK
cs => MCUBUS:inst.CS
p2[0] => MCUBUS:inst.P2[0]
p2[1] => MCUBUS:inst.P2[1]
p2[2] => MCUBUS:inst.P2[2]
p2[3] => MCUBUS:inst.P2[3]
p2[4] => MCUBUS:inst.P2[4]


|ffti|MCUBUS:inst
P0[0] <= P0[0]~0
P0[1] <= P0[1]~1
P0[2] <= P0[2]~2
P0[3] <= P0[3]~3
P0[4] <= P0[4]~4
P0[5] <= P0[5]~5
P0[6] <= P0[6]~6
P0[7] <= P0[7]~7
ALE => LATCH_ADDRES[12].CLK
ALE => LATCH_ADDRES[11].CLK
ALE => LATCH_ADDRES[10].CLK
ALE => LATCH_ADDRES[9].CLK
ALE => LATCH_ADDRES[8].CLK
ALE => LATCH_ADDRES[7].CLK
ALE => LATCH_ADDRES[6].CLK
ALE => LATCH_ADDRES[5].CLK
ALE => LATCH_ADDRES[4].CLK
ALE => LATCH_ADDRES[3].CLK
ALE => LATCH_ADDRES[2].CLK
ALE => LATCH_ADDRES[1].CLK
ALE => LATCH_ADDRES[0].CLK
RD => process3~0.IN1
WR => process4~0.IN1
CLK => ADDR[9]~reg0.CLK
CLK => ADDR[8]~reg0.CLK
CLK => ADDR[7]~reg0.CLK
CLK => ADDR[6]~reg0.CLK
CLK => ADDR[5]~reg0.CLK
CLK => ADDR[4]~reg0.CLK
CLK => ADDR[3]~reg0.CLK
CLK => ADDR[2]~reg0.CLK
CLK => ADDR[1]~reg0.CLK
CLK => ADDR[0]~reg0.CLK
CLK => ADDRDATA[10]~reg0.CLK
CLK => ADDRDATA[9]~reg0.CLK
CLK => ADDRDATA[8]~reg0.CLK
CLK => ADDRDATA[7]~reg0.CLK
CLK => ADDRDATA[6]~reg0.CLK
CLK => ADDRDATA[5]~reg0.CLK
CLK => ADDRDATA[4]~reg0.CLK
CLK => ADDRDATA[3]~reg0.CLK
CLK => ADDRDATA[2]~reg0.CLK
CLK => ADDRDATA[1]~reg0.CLK
CLK => ADDRDATA[0]~reg0.CLK
CLK => DATAOUT[7].CLK
CLK => DATAOUT[6].CLK
CLK => DATAOUT[5].CLK
CLK => DATAOUT[4].CLK
CLK => DATAOUT[3].CLK
CLK => DATAOUT[2].CLK
CLK => DATAOUT[1].CLK
CLK => DATAOUT[0].CLK
CLK => OE.CLK
CLK => DATAWR[7]~reg0.CLK
CLK => DATAWR[6]~reg0.CLK
CLK => DATAWR[5]~reg0.CLK
CLK => DATAWR[4]~reg0.CLK
CLK => DATAWR[3]~reg0.CLK
CLK => DATAWR[2]~reg0.CLK
CLK => DATAWR[1]~reg0.CLK
CLK => DATAWR[0]~reg0.CLK
CLK => WROUT~reg0.CLK
CLK => ST~reg0.CLK
CS => process0~0.IN1
CS => process3~0.IN0
CS => process4~0.IN0
CS => ADDRDATA[0]~reg0.ENA
CS => ADDRDATA[1]~reg0.ENA
CS => ADDRDATA[2]~reg0.ENA
CS => ADDRDATA[3]~reg0.ENA
CS => ADDRDATA[4]~reg0.ENA
CS => ADDRDATA[5]~reg0.ENA
CS => ADDRDATA[6]~reg0.ENA
CS => ADDRDATA[7]~reg0.ENA
CS => ADDRDATA[8]~reg0.ENA
CS => ADDRDATA[9]~reg0.ENA
CS => ADDRDATA[10]~reg0.ENA
CS => ADDR[0]~reg0.ENA
CS => ADDR[1]~reg0.ENA
CS => ADDR[2]~reg0.ENA
CS => ADDR[3]~reg0.ENA
CS => ADDR[4]~reg0.ENA
CS => ADDR[5]~reg0.ENA
CS => ADDR[6]~reg0.ENA
CS => ADDR[7]~reg0.ENA
CS => ADDR[8]~reg0.ENA
CS => ADDR[9]~reg0.ENA
FINISH => DATAOUT~7.DATAB
ADDRDATA[0] <= ADDRDATA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[1] <= ADDRDATA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[2] <= ADDRDATA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[3] <= ADDRDATA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[4] <= ADDRDATA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[5] <= ADDRDATA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[6] <= ADDRDATA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[7] <= ADDRDATA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[8] <= ADDRDATA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[9] <= ADDRDATA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRDATA[10] <= ADDRDATA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WROUT <= WROUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[0] <= DATAWR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[1] <= DATAWR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[2] <= DATAWR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[3] <= DATAWR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[4] <= DATAWR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[5] <= DATAWR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[6] <= DATAWR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAWR[7] <= DATAWR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATARD[0] => DATAOUT~31.DATAB
DATARD[1] => DATAOUT~30.DATAB
DATARD[2] => DATAOUT~29.DATAB
DATARD[3] => DATAOUT~28.DATAB
DATARD[4] => DATAOUT~27.DATAB
DATARD[5] => DATAOUT~26.DATAB
DATARD[6] => DATAOUT~25.DATAB
DATARD[7] => DATAOUT~24.DATAB
ADDR[0] <= ADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[1] <= ADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[2] <= ADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[3] <= ADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[4] <= ADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[5] <= ADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[6] <= ADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[7] <= ADDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[8] <= ADDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[9] <= ADDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATARDLOW[0] => DATAOUT~23.DATAB
DATARDLOW[1] => DATAOUT~22.DATAB
DATARDLOW[2] => DATAOUT~21.DATAB
DATARDLOW[3] => DATAOUT~20.DATAB
DATARDLOW[4] => DATAOUT~19.DATAB
DATARDLOW[5] => DATAOUT~18.DATAB
DATARDLOW[6] => DATAOUT~17.DATAB
DATARDLOW[7] => DATAOUT~16.DATAB
DATARDHIGH[0] => DATAOUT~15.DATAB
DATARDHIGH[1] => DATAOUT~14.DATAB
DATARDHIGH[2] => DATAOUT~13.DATAB
DATARDHIGH[3] => DATAOUT~12.DATAB
DATARDHIGH[4] => DATAOUT~11.DATAB
DATARDHIGH[5] => DATAOUT~10.DATAB
DATARDHIGH[6] => DATAOUT~9.DATAB
DATARDHIGH[7] => DATAOUT~8.DATAB
ST <= ST~reg0.DB_MAX_OUTPUT_PORT_TYPE
P2[0] => LATCH_ADDRES[8].DATAIN
P2[1] => LATCH_ADDRES[9].DATAIN
P2[2] => LATCH_ADDRES[10].DATAIN
P2[3] => LATCH_ADDRES[11].DATAIN
P2[4] => LATCH_ADDRES[12].DATAIN


|ffti|GEN:inst4
CLK => CONT[10].CLK
CLK => CONT[9].CLK
CLK => CONT[8].CLK
CLK => CONT[7].CLK
CLK => CONT[6].CLK
CLK => CONT[5].CLK
CLK => CONT[4].CLK
CLK => CONT[3].CLK
CLK => CONT[2].CLK
CLK => CONT[1].CLK
CLK => CONT[0].CLK
CLK => RST~reg0.CLK
CLK => START~reg0.CLK
CLK => FINISH~reg0.CLK
CLK => ADDRRD[10]~reg0.CLK
CLK => ADDRRD[9]~reg0.CLK
CLK => ADDRRD[8]~reg0.CLK
CLK => ADDRRD[7]~reg0.CLK
CLK => ADDRRD[6]~reg0.CLK
CLK => ADDRRD[5]~reg0.CLK
CLK => ADDRRD[4]~reg0.CLK
CLK => ADDRRD[3]~reg0.CLK
CLK => ADDRRD[2]~reg0.CLK
CLK => ADDRRD[1]~reg0.CLK
CLK => ADDRRD[0]~reg0.CLK
CLK => NEXTSTATE~31.IN1
CLK => CURSTATE~0.IN1
ST => NEXTSTATE~6.OUTPUTSELECT
ST => NEXTSTATE~5.OUTPUTSELECT
ST => NEXTSTATE~4.OUTPUTSELECT
ST => NEXTSTATE~3.OUTPUTSELECT
ST => NEXTSTATE~2.OUTPUTSELECT
ST => NEXTSTATE~1.OUTPUTSELECT
ST => NEXTSTATE~0.OUTPUTSELECT
ST => NEXTSTATE~14.OUTPUTSELECT
ST => NEXTSTATE~15.OUTPUTSELECT
ST => NEXTSTATE~13.OUTPUTSELECT
ST => NEXTSTATE~12.OUTPUTSELECT
ST => NEXTSTATE~11.OUTPUTSELECT
ST => NEXTSTATE~10.OUTPUTSELECT
ST => NEXTSTATE~9.OUTPUTSELECT
ST => NEXTSTATE~8.OUTPUTSELECT
ST => NEXTSTATE~7.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~22.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~21.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~20.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~19.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~18.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~17.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~16.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~29.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~28.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~27.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~26.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~25.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~24.OUTPUTSELECT
INPUTBUSY => NEXTSTATE~23.OUTPUTSELECT
FINISH <= FINISH~reg0.DB_MAX_OUTPUT_PORT_TYPE
RST <= RST~reg0.DB_MAX_OUTPUT_PORT_TYPE
START <= START~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[0] <= ADDRRD[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[1] <= ADDRRD[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[2] <= ADDRRD[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[3] <= ADDRRD[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[4] <= ADDRRD[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[5] <= ADDRRD[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[6] <= ADDRRD[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[7] <= ADDRRD[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[8] <= ADDRRD[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[9] <= ADDRRD[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRRD[10] <= ADDRRD[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ffti|cfft1024X12:inst1
clk => cfft:aCfft.clk
rst => cfft:aCfft.rst
start => cfft:aCfft.start
invert => cfft:aCfft.invert
Iin[0] => cfft:aCfft.Iin[0]
Iin[1] => cfft:aCfft.Iin[1]
Iin[2] => cfft:aCfft.Iin[2]
Iin[3] => cfft:aCfft.Iin[3]
Iin[4] => cfft:aCfft.Iin[4]
Iin[5] => cfft:aCfft.Iin[5]
Iin[6] => cfft:aCfft.Iin[6]
Iin[7] => cfft:aCfft.Iin[7]
Qin[0] => cfft:aCfft.Qin[0]
Qin[1] => cfft:aCfft.Qin[1]
Qin[2] => cfft:aCfft.Qin[2]
Qin[3] => cfft:aCfft.Qin[3]
Qin[4] => cfft:aCfft.Qin[4]
Qin[5] => cfft:aCfft.Qin[5]
Qin[6] => cfft:aCfft.Qin[6]
Qin[7] => cfft:aCfft.Qin[7]
inputbusy <= cfft:aCfft.inputbusy
outdataen <= cfft:aCfft.outdataen
Iout[0] <= cfft:aCfft.Iout[0]
Iout[1] <= cfft:aCfft.Iout[1]
Iout[2] <= cfft:aCfft.Iout[2]
Iout[3] <= cfft:aCfft.Iout[3]
Iout[4] <= cfft:aCfft.Iout[4]
Iout[5] <= cfft:aCfft.Iout[5]
Iout[6] <= cfft:aCfft.Iout[6]
Iout[7] <= cfft:aCfft.Iout[7]
Iout[8] <= cfft:aCfft.Iout[8]
Iout[9] <= cfft:aCfft.Iout[9]
Qout[0] <= cfft:aCfft.Qout[0]
Qout[1] <= cfft:aCfft.Qout[1]
Qout[2] <= cfft:aCfft.Qout[2]
Qout[3] <= cfft:aCfft.Qout[3]
Qout[4] <= cfft:aCfft.Qout[4]
Qout[5] <= cfft:aCfft.Qout[5]
Qout[6] <= cfft:aCfft.Qout[6]
Qout[7] <= cfft:aCfft.Qout[7]
Qout[8] <= cfft:aCfft.Qout[8]
Qout[9] <= cfft:aCfft.Qout[9]
OutPosition[0] <= cfft:aCfft.OutPosition[0]
OutPosition[1] <= cfft:aCfft.OutPosition[1]
OutPosition[2] <= cfft:aCfft.OutPosition[2]
OutPosition[3] <= cfft:aCfft.OutPosition[3]
OutPosition[4] <= cfft:aCfft.OutPosition[4]
OutPosition[5] <= cfft:aCfft.OutPosition[5]
OutPosition[6] <= cfft:aCfft.OutPosition[6]
OutPosition[7] <= cfft:aCfft.OutPosition[7]
OutPosition[8] <= cfft:aCfft.OutPosition[8]
OutPosition[9] <= cfft:aCfft.OutPosition[9]


|ffti|cfft1024X12:inst1|cfft:aCfft
clk => rofactor:arofactor.clk
clk => mulfactor:amulfactor.clk
clk => div4limit:Qlimit.clk
clk => div4limit:Ilimit.clk
clk => cfft4:acfft4.clk
clk => blockdram:Qram.clkb
clk => blockdram:Qram.clka
clk => blockdram:Iram.clkb
clk => blockdram:Iram.clka
clk => inv_reg.CLK
clk => address:Aaddress.clk
rst => rofactor:arofactor.rst
rst => mulfactor:amulfactor.rst
rst => cfft4:acfft4.rst
rst => inv_reg.ACLR
rst => address:Aaddress.rst
start => address:Aaddress.start
start => inv_reg.ENA
invert => inv_reg.DATAIN
Iin[0] => address:Aaddress.Iin[0]
Iin[1] => address:Aaddress.Iin[1]
Iin[2] => address:Aaddress.Iin[2]
Iin[3] => address:Aaddress.Iin[3]
Iin[4] => address:Aaddress.Iin[4]
Iin[5] => address:Aaddress.Iin[5]
Iin[6] => address:Aaddress.Iin[6]
Iin[7] => address:Aaddress.Iin[7]
Qin[0] => address:Aaddress.Qin[0]
Qin[1] => address:Aaddress.Qin[1]
Qin[2] => address:Aaddress.Qin[2]
Qin[3] => address:Aaddress.Qin[3]
Qin[4] => address:Aaddress.Qin[4]
Qin[5] => address:Aaddress.Qin[5]
Qin[6] => address:Aaddress.Qin[6]
Qin[7] => address:Aaddress.Qin[7]
inputbusy <= address:Aaddress.inputbusy
outdataen <= address:Aaddress.outdataen
Iout[0] <= cfft4:acfft4.Iout[0]
Iout[1] <= cfft4:acfft4.Iout[1]
Iout[2] <= cfft4:acfft4.Iout[2]
Iout[3] <= cfft4:acfft4.Iout[3]
Iout[4] <= cfft4:acfft4.Iout[4]
Iout[5] <= cfft4:acfft4.Iout[5]
Iout[6] <= cfft4:acfft4.Iout[6]
Iout[7] <= cfft4:acfft4.Iout[7]
Iout[8] <= cfft4:acfft4.Iout[8]
Iout[9] <= cfft4:acfft4.Iout[9]
Qout[0] <= cfft4:acfft4.Qout[0]
Qout[1] <= cfft4:acfft4.Qout[1]
Qout[2] <= cfft4:acfft4.Qout[2]
Qout[3] <= cfft4:acfft4.Qout[3]
Qout[4] <= cfft4:acfft4.Qout[4]
Qout[5] <= cfft4:acfft4.Qout[5]
Qout[6] <= cfft4:acfft4.Qout[6]
Qout[7] <= cfft4:acfft4.Qout[7]
Qout[8] <= cfft4:acfft4.Qout[8]
Qout[9] <= cfft4:acfft4.Qout[9]
OutPosition[0] <= address:Aaddress.OutPosition[0]
OutPosition[1] <= address:Aaddress.OutPosition[1]
OutPosition[2] <= address:Aaddress.OutPosition[2]
OutPosition[3] <= address:Aaddress.OutPosition[3]
OutPosition[4] <= address:Aaddress.OutPosition[4]
OutPosition[5] <= address:Aaddress.OutPosition[5]
OutPosition[6] <= address:Aaddress.OutPosition[6]
OutPosition[7] <= address:Aaddress.OutPosition[7]
OutPosition[8] <= address:Aaddress.OutPosition[8]
OutPosition[9] <= address:Aaddress.OutPosition[9]


|ffti|cfft1024X12:inst1|cfft:aCfft|address:Aaddress
clk => counter[9].CLK
clk => counter[8].CLK
clk => counter[7].CLK
clk => counter[6].CLK
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => state[3].CLK
clk => state[2].CLK
clk => state[1].CLK
clk => state[0].CLK
clk => raddr[9]~reg0.CLK
clk => raddr[8]~reg0.CLK
clk => raddr[7]~reg0.CLK
clk => raddr[6]~reg0.CLK
clk => raddr[5]~reg0.CLK
clk => raddr[4]~reg0.CLK
clk => raddr[3]~reg0.CLK
clk => raddr[2]~reg0.CLK
clk => raddr[1]~reg0.CLK
clk => raddr[0]~reg0.CLK
clk => rcounter[9].CLK
clk => rcounter[8].CLK
clk => rcounter[7].CLK
clk => rcounter[6].CLK
clk => rcounter[5].CLK
clk => rcounter[4].CLK
clk => rcounter[3].CLK
clk => rcounter[2].CLK
clk => rcounter[1].CLK
clk => rcounter[0].CLK
clk => rstate[3].CLK
clk => rstate[2].CLK
clk => rstate[1].CLK
clk => rstate[0].CLK
clk => rmask1[4].CLK
clk => rmask1[3].CLK
clk => rmask1[2].CLK
clk => rmask1[1].CLK
clk => rmask1[0].CLK
clk => rmask2[4].CLK
clk => rmask2[3].CLK
clk => rmask2[2].CLK
clk => rmask2[1].CLK
clk => rmask2[0].CLK
clk => waddr[9]~reg0.CLK
clk => waddr[8]~reg0.CLK
clk => waddr[7]~reg0.CLK
clk => waddr[6]~reg0.CLK
clk => waddr[5]~reg0.CLK
clk => waddr[4]~reg0.CLK
clk => waddr[3]~reg0.CLK
clk => waddr[2]~reg0.CLK
clk => waddr[1]~reg0.CLK
clk => waddr[0]~reg0.CLK
clk => wcounter[9].CLK
clk => wcounter[8].CLK
clk => wcounter[7].CLK
clk => wcounter[6].CLK
clk => wcounter[5].CLK
clk => wcounter[4].CLK
clk => wcounter[3].CLK
clk => wcounter[2].CLK
clk => wcounter[1].CLK
clk => wcounter[0].CLK
clk => wmask1[4].CLK
clk => wmask1[3].CLK
clk => wmask1[2].CLK
clk => wmask1[1].CLK
clk => wmask1[0].CLK
clk => wmask2[4].CLK
clk => wmask2[3].CLK
clk => wmask2[2].CLK
clk => wmask2[1].CLK
clk => wmask2[0].CLK
clk => wen~reg0.CLK
clk => factorstart~reg0.CLK
clk => cfft4start~reg0.CLK
clk => outcounter[10].CLK
clk => outcounter[9].CLK
clk => outcounter[8].CLK
clk => outcounter[7].CLK