prev_cmp_ffti.tan.qmsg

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory ramdata:inst10\|altsyncram:altsyncram_component\|altsyncram_rl92:auto_generated\|ram_block1a7~porta_address_reg0 memory ff:inst8\|lpm_ff:lpm_ff_component\|dffs\[7\] 98.5 MHz 10.152 ns Internal " "Info: Clock \"clk\" has Internal fmax of 98.5 MHz between source memory \"ramdata:inst10\|altsyncram:altsyncram_component\|altsyncram_rl92:auto_generated\|ram_block1a7~porta_address_reg0\" and destination memory \"ff:inst8\|lpm_ff:lpm_ff_component\|dffs\[7\]\" (period= 10.152 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramdata:inst10\|altsyncram:altsyncram_component\|altsyncram_rl92:auto_generated\|ram_block1a7~porta_address_reg0 1 MEM M4K_X13_Y8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y8; Fanout = 2; MEM Node = 'ramdata:inst10\|altsyncram:altsyncram_component\|altsyncram_rl92:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_rl92.tdf" "" { Text "I:/fftinterface/db/altsyncram_rl92.tdf" 287 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns ff:inst8\|lpm_ff:lpm_ff_component\|dffs\[7\] 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'ff:inst8\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.779 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 1332 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1332; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 224 -296 -128 240 "clk" "" } { 432 -110 -64 448 "clk" "" } { 552 248 288 568 "clk" "" } { 488 648 688 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.708 ns) 2.779 ns ff:inst8\|lpm_ff:lpm_ff_component\|dffs\[7\] 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(0.602 ns) + CELL(0.708 ns) = 2.779 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'ff:inst8\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.310 ns" { clk ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 78.34 % ) " "Info: Total cell delay = 2.177 ns ( 78.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.66 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk clk~out0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.793 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 1332 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1332; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 224 -296 -128 240 "clk" "" } { 432 -110 -64 448 "clk" "" } { 552 248 288 568 "clk" "" } { 488 648 688 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.722 ns) 2.793 ns ramdata:inst10\|altsyncram:altsyncram_component\|altsyncram_rl92:auto_generated\|ram_block1a7~porta_address_reg0 2 MEM M4K_X13_Y8 2 " "Info: 2: + IC(0.602 ns) + CELL(0.722 ns) = 2.793 ns; Loc. = M4K_X13_Y8; Fanout = 2; MEM Node = 'ramdata:inst10\|altsyncram:altsyncram_component\|altsyncram_rl92:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.324 ns" { clk ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_rl92.tdf" "" { Text "I:/fftinterface/db/altsyncram_rl92.tdf" 287 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 78.45 % ) " "Info: Total cell delay = 2.191 ns ( 78.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.55 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~out0 ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk clk~out0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~out0 ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_rl92.tdf" "" { Text "I:/fftinterface/db/altsyncram_rl92.tdf" 287 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "db/altsyncram_rl92.tdf" "" { Text "I:/fftinterface/db/altsyncram_rl92.tdf" 287 2 0 } } { "lpm_ff.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk clk~out0 ff:inst8|lpm_ff:lpm_ff_component|dffs[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~out0 ramdata:inst10|altsyncram:altsyncram_component|altsyncram_rl92:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ale " "Info: No valid register-to-register data paths exist for clock \"ale\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "MCUBUS:inst\|DATAOUT\[7\] rd clk 8.248 ns register " "Info: tsu for register \"MCUBUS:inst\|DATAOUT\[7\]\" (data pin = \"rd\", clock pin = \"clk\") is 8.248 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.993 ns + Longest pin register " "Info: + Longest pin to register delay is 10.993 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rd 1 PIN PIN_76 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_76; Fanout = 2; PIN Node = 'rd'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 424 -360 -192 440 "rd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.412 ns) + CELL(0.442 ns) 7.323 ns MCUBUS:inst\|DATAOUT\[1\]~2429 2 COMB LC_X22_Y6_N8 8 " "Info: 2: + IC(5.412 ns) + CELL(0.442 ns) = 7.323 ns; Loc. = LC_X22_Y6_N8; Fanout = 8; COMB Node = 'MCUBUS:inst\|DATAOUT\[1\]~2429'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.854 ns" { rd MCUBUS:inst|DATAOUT[1]~2429 } "NODE_NAME" } } { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.803 ns) + CELL(0.867 ns) 10.993 ns MCUBUS:inst\|DATAOUT\[7\] 3 REG LC_X16_Y7_N9 1 " "Info: 3: + IC(2.803 ns) + CELL(0.867 ns) = 10.993 ns; Loc. = LC_X16_Y7_N9; Fanout = 1; REG Node = 'MCUBUS:inst\|DATAOUT\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.670 ns" { MCUBUS:inst|DATAOUT[1]~2429 MCUBUS:inst|DATAOUT[7] } "NODE_NAME" } } { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 25.27 % ) " "Info: Total cell delay = 2.778 ns ( 25.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.215 ns ( 74.73 % ) " "Info: Total interconnect delay = 8.215 ns ( 74.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.993 ns" { rd MCUBUS:inst|DATAOUT[1]~2429 MCUBUS:inst|DATAOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.993 ns" { rd rd~out0 MCUBUS:inst|DATAOUT[1]~2429 MCUBUS:inst|DATAOUT[7] } { 0.000ns 0.000ns 5.412ns 2.803ns } { 0.000ns 1.469ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 1332 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1332; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 224 -296 -128 240 "clk" "" } { 432 -110 -64 448 "clk" "" } { 552 248 288 568 "clk" "" } { 488 648 688 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MCUBUS:inst\|DATAOUT\[7\] 2 REG LC_X16_Y7_N9 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y7_N9; Fanout = 1; REG Node = 'MCUBUS:inst\|DATAOUT\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk MCUBUS:inst|DATAOUT[7] } "NODE_NAME" } } { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk MCUBUS:inst|DATAOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 MCUBUS:inst|DATAOUT[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.993 ns" { rd MCUBUS:inst|DATAOUT[1]~2429 MCUBUS:inst|DATAOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.993 ns" { rd rd~out0 MCUBUS:inst|DATAOUT[1]~2429 MCUBUS:inst|DATAOUT[7] } { 0.000ns 0.000ns 5.412ns 2.803ns } { 0.000ns 1.469ns 0.442ns 0.867ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk MCUBUS:inst|DATAOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 MCUBUS:inst|DATAOUT[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk p0\[4\] MCUBUS:inst\|OE 8.562 ns register " "Info: tco from clock \"clk\" to destination pin \"p0\[4\]\" through register \"MCUBUS:inst\|OE\" is 8.562 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 1332 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1332; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 224 -296 -128 240 "clk" "" } { 432 -110 -64 448 "clk" "" } { 552 248 288 568 "clk" "" } { 488 648 688 504 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MCUBUS:inst\|OE 2 REG LC_X22_Y6_N6 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X22_Y6_N6; Fanout = 1; REG Node = 'MCUBUS:inst\|OE'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk MCUBUS:inst|OE } "NODE_NAME" } } { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk MCUBUS:inst|OE } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 MCUBUS:inst|OE } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.556 ns + Longest register pin " "Info: + Longest register to pin delay is 5.556 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MCUBUS:inst\|OE 1 REG LC_X22_Y6_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y6_N6; Fanout = 1; REG Node = 'MCUBUS:inst\|OE'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { MCUBUS:inst|OE } "NODE_NAME" } } { "MCUBUS.vhd" "" { Text "I:/fftinterface/MCUBUS.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.114 ns) 0.637 ns MCUBUS:inst\|process0~0 2 COMB LC_X22_Y6_N4 8 " "Info: 2: + IC(0.523 ns) + CELL(0.114 ns) = 0.637 ns; Loc. = LC_X22_Y6_N4; Fanout = 8; COMB Node = 'MCUBUS:inst\|process0~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.637 ns" { MCUBUS:inst|OE MCUBUS:inst|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.840 ns) + CELL(2.079 ns) 5.556 ns p0\[4\] 3 PIN PIN_71 0 " "Info: 3: + IC(2.840 ns) + CELL(2.079 ns) = 5.556 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'p0\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.919 ns" { MCUBUS:inst|process0~0 p0[4] } "NODE_NAME" } } { "ffti.bdf" "" { Schematic "I:/fftinterface/ffti.bdf" { { 360 264 440 376 "p0\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 39.47 % ) " "Info: Total cell delay = 2.193 ns ( 39.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.363 ns ( 60.53 % ) " "Info: Total interconnect delay = 3.363 ns ( 60.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.556 ns" { MCUBUS:inst|OE MCUBUS:inst|process0~0 p0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.556 ns" { MCUBUS:inst|OE MCUBUS:inst|process0~0 p0[4] } { 0.000ns 0.523ns 2.840ns } { 0.000ns 0.114ns 2.079ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk MCUBUS:inst|OE } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 MCUBUS:inst|OE } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.556 ns" { MCUBUS:inst|OE MCUBUS:inst|process0~0 p0[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.556 ns" { MCUBUS:inst|OE MCUBUS:inst|process0~0 p0[4] } { 0.000ns 0.523ns 2.840ns } { 0.000ns 0.114ns 2.079ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}