sdram_samsung.v

三星SDRAM的verilog模型的完整源码

		TADDR = CUR_TIME;
	end

always @( negedge rasb or posedge rasb)
	begin
		CUR_TIME = $realtime;
		if( PWR == `TRUE && CSB_FLAG == `LOW )
			if( pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
				$display("Warning: RASB hold violation at %t", CUR_TIME);
		if(rasb)
			RASB_FLAG = `HIGH;
		TRASB = CUR_TIME;
	end

always @( negedge casb or posedge casb)
	begin
		CUR_TIME = $realtime;
		if( PWR == `TRUE && CSB_FLAG == `LOW )
			if( pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
				$display("Warning: CASB hold violation at %t", CUR_TIME);
		if(casb)
			CASB_FLAG = `HIGH;
		TCASB = CUR_TIME;
	end

always @( negedge csb or posedge csb)
	begin
		CUR_TIME = $realtime;
		if( csb )
			CSB_FLAG <= #(CUR_TIME - TCLK_H + `tSH) csb;
		if( PWR == `TRUE && pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
			$display("Warning: CSB hold violation at %t", CUR_TIME);
		TCSB = CUR_TIME;
	end

always @( negedge web or posedge web)
	begin
		CUR_TIME = $realtime;
		if( PWR == `TRUE && CSB_FLAG == `LOW )
			if( pcke == `HIGH && CUR_TIME - TCLK_H < `tSH-`MARGIN )
				$display("Warning: WEB hold violation at %t", CUR_TIME);
		if(web)
			WEB_FLAG = `HIGH;
		else
			WEB_FLAG = `LOW;
		TWEB = CUR_TIME;
	end

always @(dqi)
	begin
		if( WRITE_MODE )
		begin
			CUR_TIME = $realtime;
			if( CUR_TIME - TCLK_H < `tSH-`MARGIN )
				$display("Warning: DQi hold violation at %t", CUR_TIME);
		end
		TDQI = $realtime;
	end

always @(dqm) begin
  CUR_TIME = $realtime;
  if (PWR == `TRUE)
	for (i = 0; i < `nDQM; i = i + 1) begin
	  if (CUR_TIME - TCLK_H < `tSH-`MARGIN && pcke == `HIGH)
		$display("Warning: DQM(%d) hold violation at %t", i, CUR_TIME);
	  TDQM[i] = $realtobits(CUR_TIME);
	end
end


/*
 *-----------------------------------------------------
 *	 power up check routine							
 *-----------------------------------------------------
 */

initial
	begin
		auto_cnt = -1;
		PWR = `FALSE;
		if(pwrup_check)
		fork
			@(posedge clk or negedge clk) PWR <= #0 `TRUE;
			begin
				#pwrup_time auto_cnt = 0;
				Mode = `INITIAL;
			end
		join
		else
		begin
			@(posedge clk or negedge clk);
			auto_cnt = 2;
			pwrup_done = `TRUE;
			PWR <= #0 `TRUE;
`ifdef v		$display("-- power up check routine skipped");
`endif
		end
	end

/*
 *-----------------------------------------------------
 *	 MRS(mode register set) 
 *-----------------------------------------------------
 */

always	@(modeset)
	begin : mrs_op
		if( &precharge_flag == 1'b1)
		begin
			$display("Warning: Illegal command in precharge operation at %t", CUR_TIME);
			disable mrs_op;
		end

		if (|Mode == 1'b0)
			$display(">> MODE register set at	%t", CUR_TIME);
		else
			begin 
				$display("Warning: Illegal MRS command at %t",CUR_TIME);
				disable mrs_op;
			end

// mode initialization
		MRS_SET    = `FALSE;

		begin
			if(~|RFU)
			begin  // {
				case(addr[2:0]) // burst length programming
					3'b000:begin		
						BL = 1;	
						WBL = 1;	
						$display("-- burst length = 1");
					end
					3'b001:begin
						BL = 2;
						WBL = 2;
						$display("-- burst length = 2");
					end
					3'b010:begin
						BL = 4;
						WBL = 4;
						$display("-- burst length = 4");
					end
					3'b011:begin
						BL = 8;
						WBL = 8;
						$display("-- burst length = 8");
					end
					3'b111:begin // added
						BL = `PAGEDEPTH;
                        WBL = `PAGEDEPTH;
                        $display("-- burst length = %d", `PAGEDEPTH);
                    end
					default	$display("Warning: Invalid Burst length!");
				endcase
`endprotect
	
				if(addr[3] && BL != `PAGEDEPTH)		// burst type  programming
				begin
					burst_type = 1'b1;   
					$display("-- burst type   = interleave.");
				end
				else
				begin
					`ifdef M16G4_M64G3		// jhkim(8.14)
						if (addr[3] && BL == `PAGEDEPTH) begin
						    $display("Warning: interleave mode does not support Full page Mode");
							$display("         interleave mode will be changed to sequential mode");
						end
					`endif
					burst_type = 1'b0;
					$display("-- burst type   = sequential.");
				end
	
				case(addr[6:4])		// CAS latency programming
					3'b001:begin	
					`ifdef NO_CL1
						  $display("Warning: cas latency 1 is not supported in 16M 4Gen. & 64M 3 Gen.");
					`else
						tSAC = `tSAC1; CL=1; tSHZ = `tSHZ1; 
						if( TCC_P < `tCC1-`MARGIN )
							$display("Warning: clock minimun cycle violation at cas latency=1");
						  $display("-- cas latency  = 1");
					`endif
					end 
					3'b010:begin
					`ifdef NO_CL2 //KyW
						  $display("Warning: cas latency 2 is not supported in this device.");
					`else
					   tSAC = `tSAC2; CL=2; tSHZ = `tSHZ2; 
						if( TCC_P < `tCC2-`MARGIN )
							$display("Warning: clock minimun cycle violation at cas latency=2");
					   $display("-- cas latency  = 2");
					`endif
					end
					3'b011:begin
					`ifdef NO_CL3 //KyW
						  $display("Warning: cas latency 3 is not supported in this device.");
					`else
					   tSAC = `tSAC3; CL=3; tSHZ = `tSHZ3; 
						if( TCC_P < `tCC3-`MARGIN )
							$display("Warning: clock minimun cycle violation at cas latency=3");
					   $display("-- cas latency  = 3");
					`endif
					end
					default	$display("Warning: Invalid CAS latency!");
				endcase
	
				if(addr[9])
				begin
					$display("-- Burst read single bit write mode");
					WBL = 1;
				end
`ifdef NOKIA
				REF16M_MODE = `FALSE;
				REF32M_MODE = `FALSE;
`endif
`ifdef MOBILE
				REF4BANK = `TRUE;
				REF2BANK = `FALSE;
				REF1BANK = `FALSE;
`endif
			end 
`ifdef NOKIA
			else if (addr[8:7] === 2'b01) begin
				if (addr[6:4] === 3'b000) begin
					if (addr[3] === 1'b0) begin
						$display("-- Partial Refresh mode (16M)");
						REF16M_MODE = `TRUE;
						REF32M_MODE = `FALSE;
					end
					else if (addr[3] === 1'b1) begin
						$display("-- Partial Refresh mode (32M)");
						REF32M_MODE = `TRUE;
						REF16M_MODE = `FALSE;
					end
				end
				else if (addr[4] === 1'b1) begin
					if (addr[2] === 1'b0) $display("-- VREFi is set to 1.4V");
					if (addr[2] === 1'b1) $display("-- VREFi is set to 0.9V");
				end
			end
`endif
`ifdef MOBILE
		else if (ba[1] === 1'b1 && ba[0] === 1'b0) begin //Extended MRS for Mobile DRAM
			case(addr[6:5]) // Drive Strength
					2'b00:
						$display("-- Full drive strength");
					2'b01:
						$display("-- Half drive strength");
					default	$display("Warning: Invalid drive strength address!");
			endcase
			case(addr[4:3]) // TCSR
					2'b00:
						$display("-- TCSR (46'C~70'C) mode");
					2'b01:
						$display("-- TCSR (16'C~45'C) mode");
					2'b10:
						$display("-- TCSR (-25'C~15'C) mode");
					2'b11:
						$display("-- TCSR (71'C~85'C) mode");
					default	$display("Warning: Invalid TCSR address!");
			endcase
			case(addr[2:0]) // PASR
					3'b000: begin
						$display("-- PASR (4 banks) mode");
						REF4BANK = `TRUE;
						REF2BANK = `FALSE;
						REF1BANK = `FALSE;
					end
					3'b001: begin
						$display("-- PASR (2 banks) mode");
						REF4BANK = `FALSE;
						REF2BANK = `TRUE;
						REF1BANK = `FALSE;
					end
					3'b010: begin
						$display("-- PASR (1 banks) mode");
						REF4BANK = `FALSE;
						REF2BANK = `FALSE;
						REF1BANK = `TRUE;
					end
					default	$display("Warning: Invalid PASR address!");
			endcase
		end
`endif
			else
			begin
				$display("-- reserved for future use !!");
				$display("-- check address: [11,10,8,7] = %b",RFU);
			end

			`ifdef M16G4_M64G3
			  MRS_SET <= repeat (2) @(negedge pclk)  `TRUE; // From 3 -> 2
			`else
			  MRS_SET <= repeat (2) @(negedge pclk)  `TRUE; // From 3 -> 2
			`endif
		end 
	end

`protect
/*
 *-----------------------------------------------------
 *	 ACTIVE command									
 *-----------------------------------------------------
 */

// In active command, bank is selected in accordance with A11 address.

always	@(active)
	begin : active_op
		integer bank_id;
		reg		[8*8:1] str;

		if(CUR_TIME - TRAS_P < `tRRD-`MARGIN)
		begin
			$display("Warning: tRRD violation at %t", CUR_TIME);
			disable active_op;
		end

		r_bank_addr = ba;

		bank_id = BankSelect(ba);
		str = PrintBank(ba);

		//if(CUR_TIME - $bitstoreal(TPRE_P[bank_id]) < `tRP-`MARGIN)
		if ((bank_id == 0) && (CUR_TIME - TPRE_P0 < `tRP-`MARGIN) ||
			(bank_id == 1) && (CUR_TIME - TPRE_P1 < `tRP-`MARGIN) ||
			(bank_id == 2) && (CUR_TIME - TPRE_P2 < `tRP-`MARGIN) ||
			(bank_id == 3) && (CUR_TIME - TPRE_P3 < `tRP-`MARGIN))
		begin
			$display("Warning: tRP violation at %t", CUR_TIME);
			disable active_op;
		end
		//if(CUR_TIME - $bitstoreal(TRAS_PP[bank_id]) < `tRC-`MARGIN)	// 2.27
		if ((bank_id == 0) && (CUR_TIME - TRAS_PP0 < `tRC-`MARGIN) ||
			(bank_id == 1) && (CUR_TIME - TRAS_PP1 < `tRC-`MARGIN) ||
			(bank_id == 2) && (CUR_TIME - TRAS_PP2 < `tRC-`MARGIN) ||
			(bank_id == 3) && (CUR_TIME - TRAS_PP3 < `tRC-`MARGIN))
		begin
			$display("Warning: tRC violation at %t", CUR_TIME);
			disable active_op;
		end

		if(Mode[bank_id] == `TRUE)
		begin
			$display("Warning: Illegal active (%0s is not precharged) at %t",str,CUR_TIME);
		end
		else
		begin
/*
			md = Mode;
			md[bank_id] = 1;
			Mode = md;
*/
			Mode[bank_id] = 1'b1;
`ifdef v		$display(">> active (%0s) at %t", str, CUR_TIME);
`endif
			//TRAS_PP[bank_id] = $realtobits(CUR_TIME);			// save current time for tRCD,tRC check.
			case(bank_id)//TRAS_PP
				'd0:	TRAS_PP0 = CUR_TIME;
				'd1:	TRAS_PP1 = CUR_TIME;
				'd2:	TRAS_PP2 = CUR_TIME;
				'd3:	TRAS_PP3 = CUR_TIME;
			endcase//TRAS_PP

			r_addr_[bank_id] = addr[`ADDRTOP:0];  // check in 64M 2bank
        end
		//TRAS_PP[bank_id] = $realtobits(CUR_TIME);			// save current time for tRCD,tRC check.
			case(bank_id)//TRAS_PP
				'd0:	TRAS_PP0 = CUR_TIME;
				'd1:	TRAS_PP1 = CUR_TIME;
				'd2:	TRAS_PP2 = CUR_TIME;
				'd3:	TRAS_PP3 = CUR_TIME;
			endcase//TRAS_PP
		TRAS_P = CUR_TIME;

	end  // active operation

/*
 *-----------------------------------------------------
 *	 READ command									  
 *-----------------------------------------------------
 */

always	@(read)
	begin :read_block
		integer bank_id;
		reg		[8*8:1] str;

		if(CUR_TIME - TCAS_P < `tCCD-`MARGIN)
		begin
			$display("Warning: tCCD violation at %t", CUR_TIME);
			disable read_block;
		end

	`ifdef M512_M1024_X4
		c_addr = {addr[12:11],addr[`nCOL-3:0]};
	`else
	`ifdef M512_M1024_X8
		c_addr = {addr[11],addr[`nCOL-2:0]};
	`else
	`ifdef M128_M256_X4 // 98.6.30 BYC
		c_addr = {addr[11],addr[`nCOL-2:0]};
	`else
		c_addr = addr[`BIT_C];
	`endif
	`endif
	`endif
		c_bank_addr = ba;

		bank_id = BankSelect(ba);
		str = PrintBank(ba);
		//if(CUR_TIME - $bitstoreal(TRAS_PP[bank_id]) < `tRCD-`MARGIN)
		if ((bank_id == 0) && (CUR_TIME - TRAS_PP0 < `tRCD-`MARGIN) ||
			(bank_id == 1) && (CUR_TIME - TRAS_PP1 < `tRCD-`MARGIN) ||
			(bank_id == 2) && (CUR_TIME - TRAS_PP2 < `tRCD-`MARGIN) ||
			(bank_id == 3) && (CUR_TIME - TRAS_PP3 < `tRCD-`MARGIN))
		begin
			$display("Warning: tRCD violation at %t", CUR_TIME);
			disable read_block;
		end
		r_addr = r_addr_[bank_id];
`endprotect

		if(Mode[bank_id] == `TRUE)
		begin
		    if( addr[`ADDR_AP] == `TRUE)
		    begin
`ifdef v			$display(">> read with auto precharge(%0s) at 	%t",str,CUR_TIME);
`endif
				auto_flag[bank_id] <= @(negedge pclk) `TRUE;
				rd_autoprech_reg <= @(negedge pclk) ba;
			end
		    else begin
`ifdef v		    $display(">> read (%0s) at %t ",str,CUR_TIME);
`endif
				auto_flag[bank_id] <= @(negedge pclk) `FALSE;
			end
		end 

		else begin
`ifdef v		$display("Illegal Read %0s is not activated",str);
`endif
			disable read_block;
		end

		READ_MODE = `TRUE;	// read operation start
		TCAS_P = CUR_TIME;

		m_addr = {r_addr, c_addr};

		if(~burst_type)
			increment_read;
		else	
			interleave_read;

		`ifdef M16G4_M64G3
		`else
		  if( auto_flag[bank_id] )
		  begin
			if( BL != 1)	
 				auto_flagx <= @(negedge pclk) `TRUE;
			->autostart;
		  end
		`endif

		read_task;			// task call

		READ_MODE = `FALSE;   // read operation end.
//        last_rw = CUR_TIME;
		last_rw = TCLK_H;

		if( auto_flag[bank_id] )
		begin
//			rd_autoprech_reg = c_bank_addr;
			if ({CSB_FLAG,RASB_FLAG,CASB_FLAG} == 3'b010 && bank_id === ba)
				$display($time, " Warning: For actual device, this gapless command would be illegal");
			else
				->rd_autoprecharge;
		end
	end

/*
 *-----------------------------------------------------