sdram_samsung.v

三星SDRAM的verilog模型的完整源码

  `ifdef M256
    	`include "m256.ac"
  `endif
*/

  parameter       pwrup_time = 200000, pwrup_check = 0;

wire     [`nBank/2 + `ADDRTOP : 0] addr;
assign addr = {ba, ad};

wire	[`BIT]	dqi;
`ifdef DYMEM
initial begin
	$damem_declare("mem_a", `B-1, 0, `nWORD-1, 0);
	$damem_declare("mem_b", `B-1, 0, `nWORD-1, 0);
end
`else
reg		[`BIT]	mem_a[`WORD];	// memory cell array of a bank
reg		[`BIT]	mem_b[`WORD];	// memory cell array of b bank
`endif
`ifdef NBANK4
`ifdef DYMEM
initial begin
	$damem_declare("mem_c", `B-1, 0, `nWORD-1, 0);
	$damem_declare("mem_d", `B-1, 0, `nWORD-1, 0);
end
`else
reg		[`BIT]	mem_c[`WORD];	// memory cell array of c bank
reg		[`BIT]	mem_d[`WORD];	// memory cell array of d bank
`endif
`endif

reg 	[`BIT] 	dqo, t_dqo;	// output temp. register declaration
reg		[`ADDRTOP:0]	r_addr_[`nBank-1:0];
reg		[`ADDRTOP:0]	r_addr;
reg		[`BIT_C] c_addr;	// column address
reg		[`BIT_T] m_addr; 	// merge row and column address 
reg 	[`BIT]  dout_reg[`PAGEDEPTH:0];
reg 	[`BIT]  din_rega[`PAGEDEPTH:0];	// din register for a bank
reg 	[`BIT]  din_regb[`PAGEDEPTH:0];	// din register for b bank
`ifdef NBANK4
reg 	[`BIT]  din_regc[`PAGEDEPTH:0];	// din register for c bank
reg 	[`BIT]  din_regd[`PAGEDEPTH:0];	// din register for d bank
`endif
reg 	[`BIT]  clk_dq;				
reg		ptr;

reg		[`BIT]	ZDATA;
reg		[7:0] ZBYTE;


// define mode dependency flag
`define INITIAL 0	// no bank precharge
/*
`define IDLE_AB	1	// both bank precharge
`define ACT_A   2	// a bank active and b bank precharge
`define ACT_B   3	// b bank active and a bank precharge
`define ACT_AB  4	// a & b bank active
`define IDLE_A  5   // only a bank prechage
`define IDLE_B  6   // only b bank prechage
*/

`define TRUE   1
`define FALSE  0
`define HIGH   1
`define LOW    0
`define	MARGIN	0.1

//parameter	pwrup_time = 200000, pwrup_check = 1;

/*
 *-----------------------------------------------------
 *	We know the phase of external signal 
 *	by examining the state of its flag.
 *-----------------------------------------------------
 */

reg		r_bank_addr;				// row bank check flag	
reg		[`nBank/2-1:0] c_bank_addr;				// column bank check flag	
reg		[`nBank-1:0] auto_flag;					// auto precharge flag
reg		burst_type,					// burst type flag
		auto_flagx,
		self_flag;					// auto & self refresh flag
integer	kill_bank, wr_kill_bank, rd_kill_bank;
integer	k;
reg		[`nBank-1:0] precharge_flag;			// precharge each bank check flag
reg		[`nBank/2:0] prech_reg;		// precharge mode (addr[13:12] && addr[10])
reg		[`nBank/2-1:0]	rd_autoprech_reg;
reg		[`nBank/2-1:0]	wr_autoprech_reg;
reg		[`nBank/2-1:0]	wr_autoprech_reg2;
reg		[`nBank/2-1:0]	prev_ba;		// bank address of previous command
reg		pwrup_done;
reg		[`nBank-1 : 0]	first_pre;
//reg		[8*8 : 1]	str;
integer auto_cnt;
integer i;

`ifdef M16
	wire	[3:0]	RFU = {addr[11:10], addr[8], addr[7]}; 
`endif

`ifdef M64
  `ifdef NBANK2
	wire	[3:0]	RFU = {addr[11:10], addr[8], addr[7]}; 
  `endif
  `ifdef NBANK4
	`ifdef X32
	  wire	[4:0]	RFU = {addr[12:10], addr[8], addr[7]}; 
	`else
	  wire	[5:0]	RFU = {addr[13:10], addr[8], addr[7]}; 
	`endif
  `endif
`endif

`ifdef M128 
  `ifdef NBANK4
	  wire	[5:0]	RFU = {addr[13:10], addr[8], addr[7]}; 
  `endif
`endif

`ifdef M256 
	`ifdef X32
	  wire	[5:0]	RFU = {addr[13:10], addr[8], addr[7]}; 
	`else
	  wire	[6:0]	RFU = {addr[14:10], addr[8], addr[7]}; 
	`endif
`endif

`ifdef M512 // 98.6.30 BYC
	wire	[6:0]	RFU = {addr[14:10], addr[8], addr[7]}; 
`endif

`ifdef M1024 
	wire	[6:0]	RFU = {addr[14:10], addr[8], addr[7]}; 
`endif

reg [`nBank-1:0] Mode;			// check mode dependency
reg 	[`nBank-1:0] md;
reg		rd_reautoprecharge, wr_reautoprecharge;
`ifdef NOKIA
	reg	REF16M_MODE, REF32M_MODE;
`endif
`ifdef DPD
	`define	tDPDEXIT	200000
	reg	D_POWERDOWN, D_PDOWN_EXIT;
	integer	PROC_DPDEXIT;
`endif
`ifdef MOBILE
	reg	REF4BANK, REF2BANK, REF1BANK;
`endif
integer	BL, WBL, CL;	// burst length & cas latency
real 	tSHZ;			// clk to output in hi-Z
real	tSAC;			// clk to valid output
reg	write_event;//KyW ... 0408 for VCS

event
	active,		// main operation of SDRAM
	modeset,
	read,
	dqo_event,
	write,
	flush_write,
	precharge,
	rd_autoprecharge,
	wr_autoprecharge,
	wr_autoprecharge2,
	precharge_start,
	precharge_flag_kill,
	wr_precharge_flag_kill,
	rd_precharge_flag_kill,
	autorefresh,
	autostart,
	selfrefresh,
`ifdef DPD
	deeppowerdown,
	d_pdown_exit,
`endif
	selfexit;

`protect



`include "init_samsung_sdram.v"


// initialize each flag
initial	
	begin
		for (i = 0; i < `nBank; i = i + 1)
		  auto_flag[i]  = `FALSE;
		auto_flagx = `FALSE;
		rd_reautoprecharge =`FALSE;
		wr_reautoprecharge =`FALSE;
		self_flag  = `FALSE;
		pwrup_done = `FALSE;
		Mode = `nBank'b0;

		for(i = 0; i < `nBank; i = i + 1)
		begin
			first_pre[i]  = `TRUE;
			precharge_flag[i] = `FALSE;
		end

		ZBYTE = 8'bz;
	    for (i = 0; i < `B; i = i + 1) begin
			ZDATA[i] = 1'bz;
		end
	end

//--------------------------------------------------------------
//---------    TIMING VIOLATION CHECK ROUTINE
//--------------------------------------------------------------

real  CUR_TIME, TCKE, TADDR, TRASB, TCASB, TCSB, TWEB, TDQI, TCLK_H, TCLK_L, 
	  TCC_P, pclk_high, last_read, last_rw;

reg [63:0] TDQM[`nDQM-1:0];

//real  TRAS_P, TCAS_P, TRASA_P, TRASB_P, TPREA_P, TPREB_P, TSELF, TSEXIT;
// 4 bank
real  TRAS_P, TCAS_P, TSELF, TSEXIT;
//reg  [63:0] TRAS_PP [`nBank-1:0];	
//reg  [63:0] TPRE_P  [`nBank-1:0];
real	TRAS_PP0, TRAS_PP1, TRAS_PP2, TRAS_PP3;
real	TPRE_P0, TPRE_P1, TPRE_P2, TPRE_P3;

reg   CKE_FLAG, CSB_FLAG, RASB_FLAG, CASB_FLAG, WEB_FLAG;

//event MRS, ACTIVE;
reg   MRS_SET, WRITE_MODE, READ_MODE, UNMODE, POWERDOWN_MODE, POWERDOWN_MODE1,//KyW ... 0928 for NOKIA claim
	  SUSPEND_MODE, AUTOREF_MODE, SELFREF_MODE;
reg   PWR, INIT;


`define NOP   (RASB_FLAG == `HIGH && CASB_FLAG == `HIGH && WEB_FLAG == `HIGH)
`define NOP1  (RASB_FLAG == `HIGH && CASB_FLAG == `HIGH)
/*
 *-----------------------------------------------------
 *	 wire declaration 
 *-----------------------------------------------------
 */

reg      pcke;
reg [`nDQM-1:0] dqm_r;
reg [`nDQM-1:0] dqm_ri;

reg      data_read;
reg      tdata_read;
reg [`BIT] clkh_dq;
reg [2:0]  prev_com;
reg          rw_dqm;
reg        gapless;
wire     pclk = pcke & clk;
wire [2:0] com = {RASB_FLAG, CASB_FLAG, WEB_FLAG};
wire #(TCC_P+0.02) data_read_delay = data_read; // 98.6.29 BYC
`endprotect

`ifdef X32
assign   #(tSAC, tSAC, tSHZ) dqi[`B-1:`B-8]= ( data_read & ~dqm_r[3] & ~rw_dqm)?dqo[`B-1:`B-8]:ZBYTE;
assign   #(tSAC, tSAC, tSHZ) dqi[`B-9:`B-16] = ( data_read & ~dqm_r[2] & ~rw_dqm)?dqo[`B-9:`B-16]:ZBYTE;
assign   #(tSAC, tSAC, tSHZ) dqi[`B-17:`B-24]= ( data_read & ~dqm_r[1] & ~rw_dqm)?dqo[`B-17:`B-24]:ZBYTE;
assign   #(tSAC, tSAC, tSHZ) dqi[`B-25:0] = ( data_read & ~dqm_r[0] & ~rw_dqm)?dqo[`B-25:0]:ZBYTE;
`endif
`ifdef X16
assign   #(tSAC, tSAC, tSHZ) dqi[`B-1:`B-8]= ( data_read & ~dqm_r[1] & ~rw_dqm)?dqo[`B-1:`B-8]:ZBYTE;
assign   #(tSAC, tSAC, tSHZ) dqi[`HB-1:0] = ( data_read & ~dqm_r[0] & ~rw_dqm)?dqo[`B-9:0]:ZBYTE;
`endif
`ifdef X8
assign   #(tSAC, tSAC, tSHZ) dqi[`B-1:0] = ( data_read & ~dqm_r & ~rw_dqm)?dqo[`B-1:0]:ZDATA;
`endif
`ifdef X4
assign   #(tSAC, tSAC, tSHZ) dqi[`B-1:0] = ( data_read & ~dqm_r & ~rw_dqm)?dqo[`B-1:0]:ZDATA;
`endif

`protect
always @(posedge pclk) begin
    pclk_high <= #0.01 $realtime;
    clkh_dq <= #0.01 dqi;
end


always @(READ_MODE) begin
//	data_read <= repeat(CL-1) @(posedge pclk) READ_MODE;
//  VCS does not support above statement. However Verilog-XL is OK. 
//  So, I modified as following statement for VCS.
	#0.1;
	if (READ_MODE == 1'b1)
		data_read <= repeat(CL-1) @(posedge pclk) 1'b1;
	else
		data_read <= repeat(CL-1) @(posedge pclk) 1'b0;
end

always @(negedge tdata_read) begin
	data_read = tdata_read;
	tdata_read = `TRUE;
end

always @(dqo_event)
	dqo <= repeat(CL-1) @(posedge pclk) t_dqo;

/*
 *-----------------------------------------------------
 * setup hold check	
 *-----------------------------------------------------
 */

initial #0.01 pcke = cke;

initial  // time variables initialization
	begin
		$timeformat(-9, 1, " ns", 10);
		TCKE = 0;
		TADDR = 0;
		TRASB = 0;
		TCASB = 0;
		TCSB = 0;
		TWEB = 0;
		TDQI = 0;
		TCLK_H = -20;
		TCLK_L = -20;
		TRAS_P = -200;
		TCAS_P = -200;
		TSELF   = -200;
        pclk_high = -20;
        last_read = -200;
        last_rw = -20;
		for (i = 0; i < `nDQM; i = i + 1)
		  TDQM[i] = 64'b0;
// 4bank
		//TRAS_PP[0] = -200;
		//TRAS_PP[1] = -200;
		//TPRE_P[0] = -200;
		//TPRE_P[1] = -200;
		TRAS_PP0 = -200;
		TRAS_PP1 = -200;
		TPRE_P0 = -200;
		TPRE_P1 = -200;
	`ifdef NBANK4
		//TRAS_PP[2] = -200;
		//TRAS_PP[3] = -200;
		//TPRE_P[2] = -200;
		//TPRE_P[3] = -200;
		TRAS_PP2 = -200;
		TRAS_PP3 = -200;
		TPRE_P2 = -200;
		TPRE_P3 = -200;
	`endif

	end

initial  // mode register variables initialization
	begin
		RASB_FLAG = `HIGH;
		CASB_FLAG = `HIGH;
		CSB_FLAG  = `HIGH;
		WEB_FLAG  = `HIGH;
	end

initial  // mode register variables initialization
	begin
		INIT        = `TRUE;
		MRS_SET     = `FALSE;
		WRITE_MODE  = `FALSE;
		READ_MODE   = `FALSE;
		POWERDOWN_MODE = `FALSE;
		POWERDOWN_MODE1 = `FALSE;//KyW ... 0928 for NOKIA claim
		SUSPEND_MODE = `FALSE;
		AUTOREF_MODE   = `FALSE;
		SELFREF_MODE   = `FALSE;
`ifdef NOKIA
		REF16M_MODE = `FALSE;
		REF32M_MODE = `FALSE;
`endif
`ifdef MOBILE
		REF4BANK = `TRUE;
		REF2BANK = `FALSE;
		REF1BANK = `FALSE;
`endif
`ifdef DPD
		D_POWERDOWN = `FALSE;
		D_PDOWN_EXIT = `FALSE;
		PROC_DPDEXIT = 0;
`endif
		write_event = `FALSE; //KyW ... 0408 for VCS
	end

always @(POWERDOWN_MODE) POWERDOWN_MODE1 = #0.1 POWERDOWN_MODE;//KyW ... 0928 for NOKIA claim

always @( posedge clk )
	if( PWR == `TRUE )
	begin : main
		CUR_TIME = $realtime;

		if( POWERDOWN_MODE == `TRUE && CKE_FLAG == `TRUE )
		begin
			if( SELFREF_MODE == `TRUE )
			  begin
				if( CUR_TIME - TSELF < `tRASmin-`MARGIN )
				begin
				  $display("Warning: tRAS violation in self refresh at %t", CUR_TIME);
				end
				->selfexit;
`ifdef v			$display(">> self refresh exit at 	%t", CUR_TIME);
`endif
`ifdef v //			$display(">> power down exit at 	%t", CUR_TIME);
`endif
				POWERDOWN_MODE = `FALSE;
				CKE_FLAG = `FALSE;
`endprotect
				`ifdef M16G2_M641G
				  pcke <= repeat (1) @(negedge pclk)  cke;
				`else
				  #0 pcke = cke;
				`endif
				
			end
`ifdef DPD
			else if (D_POWERDOWN == `TRUE)
			begin
				->d_pdown_exit;
`ifdef v			$display(">> deep power down exit at 	%t", CUR_TIME);
`endif
				POWERDOWN_MODE = `FALSE;
				CKE_FLAG = `FALSE;
			end
`endif
			else
			  begin
				`ifdef M16G2_M641G
				  if (CUR_TIME - TCKE >= `tPDE-`MARGIN)
				`else
				  if( CUR_TIME - TCKE >= `tSS-`MARGIN )
				`endif
				begin
`ifdef v				$display(">> power down exit at 	%t", CUR_TIME);
`endif
					POWERDOWN_MODE = `FALSE;
					CKE_FLAG = `FALSE;
				    pcke <= repeat (1) @(negedge pclk)  cke; 
				end
				else
				begin
					`ifdef M16G2_M641G
					  $display("Warning: tPDE violation at %t", CUR_TIME);
					`else
					  $display("Warning: tSS Precharge Power Down Exit Setup Violation at %t",CUR_TIME);
					`endif
					disable main;
				end
			end
		end

		if( POWERDOWN_MODE == `FALSE)
		begin
			if( CUR_TIME - TCKE < `tSS-`MARGIN )	// check cke setup timing
				$display("Warning: CKE setup violation at %t", CUR_TIME);
			else if( cke && SUSPEND_MODE == `TRUE )
			begin
`ifdef v			$display(">> clock suspension exit at 	%t", CUR_TIME);
`endif
				SUSPEND_MODE = `FALSE;
				pcke <= @(negedge clk) cke;
			end
			else
				pcke <= @(negedge clk) cke;
		end

// clock timing check

			TCC_P = CUR_TIME - TCLK_H;  // saving current clock period

			if( CUR_TIME - TCLK_H < `tCCmin-`MARGIN && POWERDOWN_MODE1 == `FALSE)//KyW ... 0928 for NOKIA claim
				$display("Warning: tCCmin violation at %t", CUR_TIME);

			if( CUR_TIME - TCLK_H > `tCCmax+`MARGIN && POWERDOWN_MODE1 == `FALSE)//KyW ... 0928 for NOKIA claim
				$display("Warning: tCCmax violation at %t", CUR_TIME);
`protect
			if( CUR_TIME - TCLK_L < `tCL-`MARGIN )
				$display("Warning: tCL violation at %t", CUR_TIME);

// pcke is high
		if( pcke ) begin

// csb timing check