sum.v

H.264标准解码器全部verilog源码

		if (slice_data_state == `skip_run_duration)
			begin
				res_blk4x4_IsAllZero <= 1'b1;
				res_blk4x4_onlyDC    <= 1'b0;
			end
		else
			case (residual_state)
				`Intra16x16ACLevel_0_s:	
				begin	
					res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0;
					res_blk4x4_onlyDC	 <= (curr_DC_IsZero)? 1'b0:1'b1;
				end
				`Intra16x16ACLevel_s,`ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s:
				begin
					res_blk4x4_IsAllZero <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b1:1'b0;
					res_blk4x4_onlyDC    <= (TotalCoeff == 0)? 1'b1:1'b0;
				end
				`LumaLevel_0_s:
				begin
					res_blk4x4_IsAllZero <= 1'b1;
					res_blk4x4_onlyDC	 <= 1'b0;	
				end
				`LumaLevel_s:
				begin
					res_blk4x4_IsAllZero <= (TotalCoeff == 0 || curr_CBPLuma_IsZero)? 1'b1:1'b0;
					res_blk4x4_onlyDC	 <= 1'b0;
				end
				`ChromaACLevel_0_s:					//CodedBlockPatternChroma == 0 or 1
				if (CodedBlockPatternChroma == 0)	//CodedBlockPatternChroma == 0
					begin
						res_blk4x4_IsAllZero <= 1'b1;
						res_blk4x4_onlyDC	 <= 1'b0;
					end
				else 								//CodedBlockPatternChroma == 1
					begin
						res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0;
						res_blk4x4_onlyDC	 <= (curr_DC_IsZero)? 1'b0:1'b1;
					end
				default:
				begin
					res_blk4x4_IsAllZero <= 1'b0;
					res_blk4x4_onlyDC    <= 1'b0;
				end
			endcase
		
	reg [8:0] sum_PE0_a,sum_PE1_a,sum_PE2_a,sum_PE3_a;
	reg [7:0] sum_PE0_b,sum_PE1_b,sum_PE2_b,sum_PE3_b;
	wire sum_PE_bypass; //only one bypass signal for all sum_PE0 ~ sum_PE3
	assign sum_PE_bypass = (blk4x4_sum_counter != 3'd4 && !res_blk4x4_IsAllZero)? 1'b0:1'b1;
	
	sum_PE sum_PE0 (
		.a(sum_PE0_a),
		.b(sum_PE0_b),
		.bypass(sum_PE_bypass),
		.c(blk4x4_sum_PE0_out)
		);	
	sum_PE sum_PE1 (
		.a(sum_PE1_a),
		.b(sum_PE1_b),
		.bypass(sum_PE_bypass),
		.c(blk4x4_sum_PE1_out)
		);
	sum_PE sum_PE2 (
		.a(sum_PE2_a),
		.b(sum_PE2_b),
		.bypass(sum_PE_bypass),
		.c(blk4x4_sum_PE2_out)
		);
	sum_PE sum_PE3 (
		.a(sum_PE3_a),
		.b(sum_PE3_b),
		.bypass(sum_PE_bypass),
		.c(blk4x4_sum_PE3_out)
		);
	
	// only for statistical purpose
	// synopsys translate_off
	integer	number_of_IsAllZero;
	integer number_of_onlyDC;
	initial
		begin
			number_of_IsAllZero = 0;
			number_of_onlyDC = 0;
		end
	always @ (blk4x4_sum_counter)
		if (blk4x4_sum_counter == 3'd2)
			begin
				if (res_blk4x4_IsAllZero == 1'b1)	number_of_IsAllZero <= number_of_IsAllZero + 1;
				else if (res_blk4x4_onlyDC == 1'b1)	number_of_onlyDC 	<= number_of_onlyDC + 1;
			end
	// synopsys translate_on
		
	always @ (blk4x4_sum_counter or res_blk4x4_IsAllZero or res_blk4x4_onlyDC or curr_DC_scaled or
		IQIT_output_0  or IQIT_output_1  or IQIT_output_2  or IQIT_output_3  or 
		IQIT_output_4  or IQIT_output_5  or IQIT_output_6  or IQIT_output_7  or 
		IQIT_output_8  or IQIT_output_9  or IQIT_output_10 or IQIT_output_11 or 
		IQIT_output_12 or IQIT_output_13 or IQIT_output_14 or IQIT_output_15)
		if (res_blk4x4_IsAllZero)
			begin 	sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0;	end
		else if (res_blk4x4_onlyDC)
			begin 	sum_PE0_a <= curr_DC_scaled; sum_PE1_a <= curr_DC_scaled; 
					sum_PE2_a <= curr_DC_scaled; sum_PE3_a <= curr_DC_scaled;	end
		else 
			case (blk4x4_sum_counter)
				0:begin	sum_PE0_a <= IQIT_output_0; sum_PE1_a <= IQIT_output_1;		
						sum_PE2_a <= IQIT_output_2;	sum_PE3_a <= IQIT_output_3; end
				1:begin	sum_PE0_a <= IQIT_output_4;	sum_PE1_a <= IQIT_output_5;		
						sum_PE2_a <= IQIT_output_6;	sum_PE3_a <= IQIT_output_7; end
				2:begin	sum_PE0_a <= IQIT_output_8;	sum_PE1_a <= IQIT_output_9;		
						sum_PE2_a <= IQIT_output_10;sum_PE3_a <= IQIT_output_11; end
				3:begin	sum_PE0_a <= IQIT_output_12;sum_PE1_a <= IQIT_output_13;		
						sum_PE2_a <= IQIT_output_14;sum_PE3_a <= IQIT_output_15; end
				default:begin sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0; end
			endcase
	always @ (blk4x4_sum_counter or 
		blk4x4_pred_output0  or blk4x4_pred_output1  or blk4x4_pred_output2  or blk4x4_pred_output3  or 
		blk4x4_pred_output4  or blk4x4_pred_output5  or blk4x4_pred_output6  or blk4x4_pred_output7  or 
		blk4x4_pred_output8  or blk4x4_pred_output9  or blk4x4_pred_output10 or blk4x4_pred_output11 or 
		blk4x4_pred_output12 or blk4x4_pred_output13 or blk4x4_pred_output14 or blk4x4_pred_output15)
		case (blk4x4_sum_counter)
			0:begin	sum_PE0_b <= blk4x4_pred_output0; sum_PE1_b <= blk4x4_pred_output1;	
					sum_PE2_b <= blk4x4_pred_output2; sum_PE3_b <= blk4x4_pred_output3; end
			1:begin	sum_PE0_b <= blk4x4_pred_output4; sum_PE1_b <= blk4x4_pred_output5;	
					sum_PE2_b <= blk4x4_pred_output6; sum_PE3_b <= blk4x4_pred_output7; end
			2:begin	sum_PE0_b <= blk4x4_pred_output8; sum_PE1_b <= blk4x4_pred_output9;	
					sum_PE2_b <= blk4x4_pred_output10;sum_PE3_b <= blk4x4_pred_output11; end
			3:begin	sum_PE0_b <= blk4x4_pred_output12;sum_PE1_b <= blk4x4_pred_output13;	
					sum_PE2_b <= blk4x4_pred_output14;sum_PE3_b <= blk4x4_pred_output15; end
			default:begin sum_PE0_b <= 0; sum_PE1_b <= 0; sum_PE2_b <= 0; sum_PE3_b <= 0; end
		endcase
	//----------------------------------------------------------------------
	//sum right most column latch for Intra mbAddrA
	//----------------------------------------------------------------------
	//sum_right_column_reg:
	always @ (posedge gclk_blk4x4_sum or negedge reset_n)
		if (reset_n == 0)
			sum_right_column_reg <= 0;
		else 
			case (blk4x4_sum_counter)
				3'd0:sum_right_column_reg[7:0]   <= blk4x4_sum_PE3_out;
				3'd1:sum_right_column_reg[15:8]  <= blk4x4_sum_PE3_out;
				3'd2:sum_right_column_reg[23:16] <= blk4x4_sum_PE3_out;
			endcase
			
	//blk4x4_rec_counter_2_raster_order:
	//change from double-z order to raster order
	always @ (blk4x4_rec_counter)
		case (blk4x4_rec_counter)
			5'd2 :blk4x4_rec_counter_2_raster_order <= 5'd4;
			5'd3 :blk4x4_rec_counter_2_raster_order <= 5'd5;
			5'd4 :blk4x4_rec_counter_2_raster_order <= 5'd2;
			5'd5 :blk4x4_rec_counter_2_raster_order <= 5'd3;
			5'd10:blk4x4_rec_counter_2_raster_order <= 5'd12;
			5'd11:blk4x4_rec_counter_2_raster_order <= 5'd13;
			5'd12:blk4x4_rec_counter_2_raster_order <= 5'd10;
			5'd13:blk4x4_rec_counter_2_raster_order <= 5'd11;
			default:blk4x4_rec_counter_2_raster_order <= blk4x4_rec_counter;
		endcase
	//----------------------------------------------------------------------
	//Intra_mbAddrB_RAM write control
	//----------------------------------------------------------------------
	wire Is_blk4x4_rec_bottom;
	assign Is_blk4x4_rec_bottom = (blk4x4_rec_counter == 5'd10 || blk4x4_rec_counter == 5'd11 ||
	blk4x4_rec_counter == 5'd14 || blk4x4_rec_counter == 5'd15 || blk4x4_rec_counter == 5'd18 || 
	blk4x4_rec_counter == 5'd19 || blk4x4_rec_counter == 5'd22 || blk4x4_rec_counter == 5'd23);
	
	assign Intra_mbAddrB_RAM_wr = (mb_num_v != 4'd8 && blk4x4_sum_counter == 3'd3 && Is_blk4x4_rec_bottom && !LowerMB_IsSkip);
	assign Intra_mbAddrB_RAM_din = (Intra_mbAddrB_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0; 
	
	//	base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr
	reg [6:0] Intra_mbAddrB_RAM_addr_bp;
	always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2])
		if (Intra_mbAddrB_RAM_wr)
			begin
				if (blk4x4_rec_counter[4] == 1'b0)		Intra_mbAddrB_RAM_addr_bp <= 0;
				else if (blk4x4_rec_counter[2] == 1'b0)	Intra_mbAddrB_RAM_addr_bp <= 7'd44;
				else									Intra_mbAddrB_RAM_addr_bp <= 7'd66;
			end
		else											Intra_mbAddrB_RAM_addr_bp <= 0;
			
	//	shift pointer,x2 for chroma,x4 for luma
	wire [5:0] Intra_mbAddrB_RAM_addr_sp;
	assign Intra_mbAddrB_RAM_addr_sp = (Intra_mbAddrB_RAM_wr && blk4x4_rec_counter[4] == 1'b1)? 
										{1'b0,mb_num_h,1'b0}:{mb_num_h,2'b0};
	//	pointer for relative address of each 4x4 block inside a MB
	reg [1:0] Intra_mbAddrB_RAM_addr_ip;
	always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2:0])	
		if (Intra_mbAddrB_RAM_wr)
			begin
				if (blk4x4_rec_counter[4] == 1'b0)
					case (blk4x4_rec_counter[2:0])
						3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'd0;
						3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'd1;
						3'b110:Intra_mbAddrB_RAM_addr_ip <= 2'd2;
						3'b111:Intra_mbAddrB_RAM_addr_ip <= 2'd3;
						default:Intra_mbAddrB_RAM_addr_ip <= 0;
					endcase
				else
					Intra_mbAddrB_RAM_addr_ip <= {1'b0,blk4x4_rec_counter[0]};
			end
		else
			Intra_mbAddrB_RAM_addr_ip <= 0;
			
	assign Intra_mbAddrB_RAM_wr_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip;		
	
	/*
	// synopsys translate_off
	integer	tracefile; 
	initial
		begin
			tracefile = $fopen("nova_sum_output.log");
		end
		
	wire [6:0] mb_num;
	assign mb_num = mb_num_v * 11 + mb_num_h;
	
	wire [1:0] blk4x4_rec_counter_M4;
	assign blk4x4_rec_counter_M4 = blk4x4_rec_counter[1:0];
	
	reg [8:0] pic_num;
	always @ (reset_n or mb_num)
		if (reset_n == 1'b0)
			pic_num <= 9'b111111111;
		else if (mb_num == 0)
			pic_num <= pic_num + 1;
	
	always @ (posedge clk)
		if (blk4x4_sum_counter == 0)
			begin
				$fdisplay (tracefile,"------------------------ Pic = %3d, MB = %3d -------------------------",pic_num,mb_num);
				if (blk4x4_rec_counter < 16)
  					$fdisplay (tracefile," [Luma]   blk4x4Idx = %2d",blk4x4_rec_counter);
  				else
  					$fdisplay (tracefile," [Chroma] blk4x4Idx = %2d",blk4x4_rec_counter_M4);
				$fdisplay (tracefile," Sum  output: %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out);
			end
		else if (blk4x4_sum_counter != 3'd4)
  			$fdisplay (tracefile,"              %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out);
	// synopsys translate_on
	*/
	
endmodule

module sum_PE (a,b,bypass,c);
	input [8:0] a;	//for residual from IQIT
	input [7:0] b;	//for prediction from intra or inter
	input bypass;
	output [7:0] c;
	
	wire [9:0] sum;
	
	assign sum = (bypass)? 0:({2'b0,b} + {a[8],a});
	assign c   = (bypass)? b:((sum[9] == 1'b1)? 0:((sum[8] == 1'b1)? 8'd255:sum[7:0]));
endmodule