syntax_decoding.v

H.264标准解码器全部verilog源码

	reg [4:0] mb_type;
	reg [3:0] mb_type_general;
	reg [3:0] mb_type_general_reg;
	reg [1:0] Intra16x16_predmode;
		
	//mb_type_general
	assign mb_skip_run = (slice_data_state == `mb_skip_run_s)? exp_golomb_decoding_output[6:0]:mb_skip_run_reg; 
	always @ (slice_data_state or slice_type or exp_golomb_decoding_output or mb_type_general_reg)
		if (slice_data_state == `skip_run_duration)
			mb_type_general <= `MB_P_skip;
		else if (slice_data_state == `mb_type_s)
			begin
				if (slice_type == 2 || slice_type == 7)	//I slice
					case (exp_golomb_decoding_output)
						0:                      mb_type_general <= `MB_Intra4x4;
						1,2,3,4,13,14,15,16:    mb_type_general <= `MB_Intra16x16_CBPChroma0;
						5,6,7,8,17,18,19,20:    mb_type_general <= `MB_Intra16x16_CBPChroma1;
						9,10,11,12,21,22,23,24: mb_type_general <= `MB_Intra16x16_CBPChroma2;
						default:                mb_type_general <= `MB_Inter16x16;
					endcase
				else                                    //P slice
					case (exp_golomb_decoding_output)
						0:                      mb_type_general <= `MB_Inter16x16;
						1:                      mb_type_general <= `MB_Inter16x8;
						2:                      mb_type_general <= `MB_Inter8x16;
						3:                      mb_type_general <= `MB_P_8x8;
						4:                      mb_type_general <= `MB_P_8x8ref0;
						5:                      mb_type_general <= `MB_Intra4x4;
						6,7,8,9,18,19,20,21:    mb_type_general <= `MB_Intra16x16_CBPChroma0;
						10,11,12,13,22,23,24,25:mb_type_general <= `MB_Intra16x16_CBPChroma1;
						14,15,16,17,26,27,28,29:mb_type_general <= `MB_Intra16x16_CBPChroma0;
						default:                mb_type_general <= `MB_Inter16x8;
					endcase
			end
		else
			mb_type_general <= mb_type_general_reg;
			
	//Intra16x16_predmode
	always @ (posedge clk)
		if (reset_n == 0)
			Intra16x16_predmode <= 2'b0;
		else if (slice_data_state == `mb_type_s)
			begin
				if (slice_type == 2 || slice_type == 7)	//I slice
					begin
						if (exp_golomb_decoding_output != 0)
							case (exp_golomb_decoding_output[1:0])
								2'b00:Intra16x16_predmode <= 2'b11;
								2'b01:Intra16x16_predmode <= 2'b00;
								2'b10:Intra16x16_predmode <= 2'b01;
								2'b11:Intra16x16_predmode <= 2'b10;
							endcase
					end
				else if (exp_golomb_decoding_output[4:0] > 5) //P slice
					case (exp_golomb_decoding_output[1:0])
						2'b00:Intra16x16_predmode <= 2'b10;
						2'b01:Intra16x16_predmode <= 2'b11;
						2'b10:Intra16x16_predmode <= 2'b00;
						2'b11:Intra16x16_predmode <= 2'b01;
					endcase
			end
	
	always @ (posedge clk)
		if (reset_n == 0)
			begin
				mb_skip_run_reg <= 0;
				mb_type <= 0;
				mb_type_general_reg <= `MB_type_rst;
			end
		else 
			case (slice_data_state)
				`mb_skip_run_s:mb_skip_run_reg <= mb_skip_run;
				`skip_run_duration:
				begin
					mb_type <= 5'd31;
					mb_type_general_reg <= mb_type_general;
				end
				`mb_type_s:
				begin
					mb_type <= exp_golomb_decoding_output[4:0];
					mb_type_general_reg <= mb_type_general;
				end
				//pcm_byte_s: --> Currently no deal with it
				//coded_block_pattern_s: --> See CodedBlockPattern_decoding.v
				//mb_qp_delta_s:mb_qp_delta <= exp_golomb_decoding_output;
			endcase
	//Update MBTypeGen information
	reg [1:0] MBTypeGen_mbAddrA;
	reg MBTypeGen_mbAddrD_tmp;
	reg MBTypeGen_mbAddrD;
	reg [21:0] MBTypeGen_mbAddrB_reg;
	always @ (posedge clk)
		if (reset_n == 0)
			begin
				MBTypeGen_mbAddrA <= 0;
				MBTypeGen_mbAddrD_tmp <= 0;
				MBTypeGen_mbAddrB_reg <= 0;
			end
		else if (slice_data_state == `skip_run_duration && end_of_MB_DEC)//for P_skip
			begin
				if (mb_num_h != 10)
					MBTypeGen_mbAddrA <= `MB_addrA_addrB_P_skip;
				if (mb_num_h == 9)
					MBTypeGen_mbAddrD_tmp <= 1'b0;
				if (mb_num_v != 8)
					case (mb_num_h)
						0:MBTypeGen_mbAddrB_reg[1:0]    <= `MB_addrA_addrB_P_skip;1:MBTypeGen_mbAddrB_reg[3:2] 	 <= `MB_addrA_addrB_P_skip;
						2:MBTypeGen_mbAddrB_reg[5:4]    <= `MB_addrA_addrB_P_skip;3:MBTypeGen_mbAddrB_reg[7:6] 	 <= `MB_addrA_addrB_P_skip;
						4:MBTypeGen_mbAddrB_reg[9:8]    <= `MB_addrA_addrB_P_skip;5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_P_skip;
						6:MBTypeGen_mbAddrB_reg[13:12] 	<= `MB_addrA_addrB_P_skip;7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_P_skip;
						8:MBTypeGen_mbAddrB_reg[17:16] 	<= `MB_addrA_addrB_P_skip;9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_P_skip;
						10:MBTypeGen_mbAddrB_reg[21:20]	<= `MB_addrA_addrB_P_skip;
					endcase
			end
		else if (slice_data_state == `mb_num_update)
			begin
				if (mb_num_h != 10)
					begin
						if (mb_type_general[3] == 1'b0)
							MBTypeGen_mbAddrA <= `MB_addrA_addrB_Inter;
						else if (mb_type_general[3:2] == 2'b10)
							MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra16x16;
						else if (mb_type_general == `MB_Intra4x4)
							MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra4x4;
					end
				if (mb_num_h == 9)
					MBTypeGen_mbAddrD_tmp <= mb_type_general[3];
				if (mb_num_v != 8)
					begin
						if (mb_type_general[3] == 1'b0)
							case (mb_num_h)
								0:MBTypeGen_mbAddrB_reg[1:0]   <= `MB_addrA_addrB_Inter; 1:MBTypeGen_mbAddrB_reg[3:2]   <= `MB_addrA_addrB_Inter;
								2:MBTypeGen_mbAddrB_reg[5:4]   <= `MB_addrA_addrB_Inter; 3:MBTypeGen_mbAddrB_reg[7:6]   <= `MB_addrA_addrB_Inter;
								4:MBTypeGen_mbAddrB_reg[9:8]   <= `MB_addrA_addrB_Inter; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Inter;
								6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Inter; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Inter;
								8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Inter; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Inter;
								10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Inter;
							endcase
						else if (mb_type_general[3:2] == 2'b10)
							case (mb_num_h)
								0:MBTypeGen_mbAddrB_reg[1:0]   <= `MB_addrA_addrB_Intra16x16; 1:MBTypeGen_mbAddrB_reg[3:2]   <= `MB_addrA_addrB_Intra16x16;
								2:MBTypeGen_mbAddrB_reg[5:4]   <= `MB_addrA_addrB_Intra16x16; 3:MBTypeGen_mbAddrB_reg[7:6]   <= `MB_addrA_addrB_Intra16x16;
								4:MBTypeGen_mbAddrB_reg[9:8]   <= `MB_addrA_addrB_Intra16x16; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra16x16;
								6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra16x16; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra16x16;
								8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra16x16; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra16x16;
								10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra16x16;
							endcase
						else if (mb_type_general == `MB_Intra4x4)
							case (mb_num_h)
								0:MBTypeGen_mbAddrB_reg[1:0]   <= `MB_addrA_addrB_Intra4x4;	1:MBTypeGen_mbAddrB_reg[3:2]   <= `MB_addrA_addrB_Intra4x4;
								2:MBTypeGen_mbAddrB_reg[5:4]   <= `MB_addrA_addrB_Intra4x4;	3:MBTypeGen_mbAddrB_reg[7:6]   <= `MB_addrA_addrB_Intra4x4;
								4:MBTypeGen_mbAddrB_reg[9:8]   <= `MB_addrA_addrB_Intra4x4;	5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra4x4;
								6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra4x4; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra4x4;
								8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra4x4; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra4x4;
								10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra4x4;
							endcase
					end
			end
	
	always @ (posedge clk)
		if (reset_n == 1'b0)
			MBTypeGen_mbAddrD <= 0;
		else if (mb_num_h == 0)
			MBTypeGen_mbAddrD <= MBTypeGen_mbAddrD_tmp;
	
	//----------------------------------------------------------------------
	//mb_pred & sub_mb_pred	
	//	--> Also refer to Intra4x4_PredMode_decoding.v & Inter_mv_decoding.v
	//----------------------------------------------------------------------
	wire prev_intra4x4_pred_mode_flag;
	reg prev_intra4x4_pred_mode_flag_reg;
	wire [2:0] rem_intra4x4_pred_mode;
	reg [2:0] rem_intra4x4_pred_mode_reg;
	reg [1:0] intra_chroma_pred_mode;
	wire [7:0] mvd;
	reg [7:0] mvd_reg;
	reg [7:0] sub_mb_type_reg;
	assign prev_intra4x4_pred_mode_flag = (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)? BitStream_buffer_output[15]:prev_intra4x4_pred_mode_flag_reg;
	assign rem_intra4x4_pred_mode = (mb_pred_state == `rem_intra4x4_pred_mode_s)? BitStream_buffer_output[15:13]:rem_intra4x4_pred_mode_reg;	
	assign mvd = ((mb_pred_state == `mvd_l0_s) || (sub_mb_pred_state == `sub_mvd_l0_s))? exp_golomb_decoding_output[7:0]:mvd_reg;				
	always @ (posedge clk)
		if (reset_n == 0)
			begin
				prev_intra4x4_pred_mode_flag_reg <= 0;
				rem_intra4x4_pred_mode_reg       <= 0;
				intra_chroma_pred_mode           <= 0;
				mvd_reg                          <= 0;
				sub_mb_type_reg                  <= 0;
			end
		else
			begin
				case (mb_pred_state)
					`prev_intra4x4_pred_mode_flag_s:prev_intra4x4_pred_mode_flag_reg <= prev_intra4x4_pred_mode_flag;
					`rem_intra4x4_pred_mode_s      :rem_intra4x4_pred_mode_reg       <= rem_intra4x4_pred_mode;
					`intra_chroma_pred_mode_s      :intra_chroma_pred_mode           <= exp_golomb_decoding_output[1:0];
					//ref_idx_l0_s: --> only 1 reference frame,so never jump into this state
					`mvd_l0_s:	mvd_reg <= mvd;
				endcase
				case (sub_mb_pred_state)
					`sub_mb_type_s:
					case (mbPartIdx)
						0:sub_mb_type_reg[1:0] <= exp_golomb_decoding_output[1:0];
						1:sub_mb_type_reg[3:2] <= exp_golomb_decoding_output[1:0];
						2:sub_mb_type_reg[5:4] <= exp_golomb_decoding_output[1:0];
						3:sub_mb_type_reg[7:6] <= exp_golomb_decoding_output[1:0];
					endcase
					//sub_ref_idx_l0_s: --> only 1 reference frame,so never jump into this state
					`sub_mvd_l0_s: mvd_reg <= mvd;
				endcase
			end
	reg [2:0] NumMbPart;
	reg [2:0] NumSubMbPart;
	reg [1:0] sub_mb_type;
	always @ (sub_mb_pred_state or sub_mb_type_reg or mbPartIdx)
		if (sub_mb_pred_state == `sub_mvd_l0_s)
			case (mbPartIdx)
				0:sub_mb_type <= sub_mb_type_reg[1:0]; 
				1:sub_mb_type <= sub_mb_type_reg[3:2];
				2:sub_mb_type <= sub_mb_type_reg[5:4];
				3:sub_mb_type <= sub_mb_type_reg[7:6];
			endcase
		else
			sub_mb_type <= 0;							 
	always @ (mb_pred_state or mb_type_general or sub_mb_pred_state)
		if (mb_pred_state == `mvd_l0_s)
			case (mb_type_general)
				0:NumMbPart <= 3'd1;
				default:NumMbPart <= 3'd2;
			endcase
		else if (sub_mb_pred_state == `sub_mvd_l0_s)
			NumMbPart <= 3'd4;
		else 
			NumMbPart <= 3'd0;	
	always @ (sub_mb_pred_state or mbPartIdx or sub_mb_type_reg)
		if (sub_mb_pred_state == `sub_mvd_l0_s)
			case (mbPartIdx)
				0:
				case (sub_mb_type_reg[1:0])
					2'b00      :NumSubMbPart <= 3'd1;
					2'b01,2'b10:NumSubMbPart <= 3'd2;
					2'b11      :NumSubMbPart <= 3'd4;
				endcase
				1:
				case (sub_mb_type_reg[3:2])
					2'b00      :NumSubMbPart <= 3'd1;
					2'b01,2'b10:NumSubMbPart <= 3'd2;
					2'b11      :NumSubMbPart <= 3'd4;
				endcase
				2:
				case (sub_mb_type_reg[5:4])
					2'b00      :NumSubMbPart <= 3'd1;
					2'b01,2'b10:NumSubMbPart <= 3'd2;
					2'b11      :NumSubMbPart <= 3'd4;
				endcase
				3:
				case (sub_mb_type_reg[7:6])
					2'b00      :NumSubMbPart <= 3'd1;
					2'b01,2'b10:NumSubMbPart <= 3'd2;
					2'b11      :NumSubMbPart <= 3'd4;
				endcase
			endcase
		else
			NumSubMbPart <= 0;
			
	//mv_below8x8
	reg [3:0] mv_below8x8; 
	always @ (posedge clk)
		if (reset_n == 1'b0)
			mv_below8x8 <= 4'b0;
		else if (sub_mb_pred_state == `sub_mb_type_s)
			case (mbPartIdx)
				0:mv_below8x8[0] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; 
				1:mv_below8x8[1] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; 
				2:mv_below8x8[2] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; 
				3:mv_below8x8[3] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; 
			endcase
		else if (slice_data_state == `mb_pred || slice_data_state == `skip_run_duration)
			mv_below8x8 <= 4'b0;
			
endmodule