_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity plane_bc_precomputation is
    port(
        HV_in           : in     vl_logic_vector(14 downto 0);
        IsLuma          : in     vl_logic;
        bc_out          : out    vl_logic_vector(11 downto 0)
    );
end plane_bc_precomputation;