lcdfinal.map.qmsg

来自「用状态机实现密码锁State machine used to achieve c」· QMSG 代码 · 共 134 行 · 第 1/5 页

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "next_sub_state passed_lock.v(212) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(212): variable \"next_sub_state\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 212 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "next_sub_state passed_lock.v(181) " "Warning (10240): Verilog HDL Always Construct warning at passed_lock.v(181): inferring latch(es) for variable \"next_sub_state\", which holds its previous value in one or more paths through the always construct" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 181 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "passed_lock.v(267) " "Info (10264): Verilog HDL Case Statement information at passed_lock.v(267): all case item expressions in this case statement are onehot" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 267 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 passed_lock.v(289) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(289): truncated value with size 32 to match size of target (2)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 289 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "next_sub_state.finish passed_lock.v(232) " "Info (10041): Inferred latch for \"next_sub_state.finish\" at passed_lock.v(232)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "next_sub_state.fourth passed_lock.v(232) " "Info (10041): Inferred latch for \"next_sub_state.fourth\" at passed_lock.v(232)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "next_sub_state.third passed_lock.v(232) " "Info (10041): Inferred latch for \"next_sub_state.third\" at passed_lock.v(232)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "next_sub_state.second passed_lock.v(232) " "Info (10041): Inferred latch for \"next_sub_state.second\" at passed_lock.v(232)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "next_sub_state.first passed_lock.v(232) " "Info (10041): Inferred latch for \"next_sub_state.first\" at passed_lock.v(232)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_TEST_initial LCD_TEST_initial:u0 " "Info: Elaborating entity \"LCD_TEST_initial\" for hierarchy \"LCD_TEST_initial:u0\"" {  } { { "lcdfinal.v" "u0" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 132 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 LCD_TEST_initial.v(75) " "Warning (10230): Verilog HDL assignment warning at LCD_TEST_initial.v(75): truncated value with size 32 to match size of target (18)" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 LCD_TEST_initial.v(83) " "Warning (10230): Verilog HDL assignment warning at LCD_TEST_initial.v(83): truncated value with size 32 to match size of target (6)" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 LCD_TEST_initial.v(93) " "Warning (10230): Verilog HDL assignment warning at LCD_TEST_initial.v(93): truncated value with size 32 to match size of target (6)" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 93 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "LCD_XX LCD_TEST_initial.v(105) " "Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(105): variable \"LCD_XX\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 105 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "password LCD_TEST_initial.v(161) " "Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(161): variable \"password\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 161 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "password LCD_TEST_initial.v(162) " "Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(162): variable \"password\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 162 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "password LCD_TEST_initial.v(163) " "Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(163): variable \"password\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 163 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "password LCD_TEST_initial.v(164) " "Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(164): variable \"password\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 164 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "try_count LCD_TEST_initial.v(175) " "Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(175): variable \"try_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 175 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "LCD_TEST_initial.v(105) " "Warning (10270): Verilog HDL Case Statement warning at LCD_TEST_initial.v(105): incomplete case statement has no default case item" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 105 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "LCD_TEST_initial.v(105) " "Info (10264): Verilog HDL Case Statement information at LCD_TEST_initial.v(105): all case item expressions in this case statement are onehot" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 105 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LEDG LCD_TEST_initial.v(103) " "Warning (10240): Verilog HDL Always Construct warning at LCD_TEST_initial.v(103): inferring latch(es) for variable \"LEDG\", which holds its previous value in one or more paths through the always construct" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LUT_DATA LCD_TEST_initial.v(103) " "Warning (10240): Verilog HDL Always Construct warning at LCD_TEST_initial.v(103): inferring latch(es) for variable \"LUT_DATA\", which holds its previous value in one or more paths through the always construct" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LEDR LCD_TEST_initial.v(103) " "Warning (10240): Verilog HDL Always Construct warning at LCD_TEST_initial.v(103): inferring latch(es) for variable \"LEDR\", which holds its previous value in one or more paths through the always construct" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "LEDR\[0\] LCD_TEST_initial.v(103) " "Info (10041): Inferred latch for \"LEDR\[0\]\" at LCD_TEST_initial.v(103)" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "LEDR\[1\] LCD_TEST_initial.v(103) " "Info (10041): Inferred latch for \"LEDR\[1\]\" at LCD_TEST_initial.v(103)" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "LEDR\[2\] LCD_TEST_initial.v(103) " "Info (10041): Inferred latch for \"LEDR\[2\]\" at LCD_TEST_initial.v(103)" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}