lcdfinal.map.qmsg

来自「用状态机实现密码锁State machine used to achieve c」· QMSG 代码 · 共 134 行 · 第 1/5 页

{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "nine passed_lock.v(40) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(40): object \"nine\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 40 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "zero passed_lock.v(41) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(41): object \"zero\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 41 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(32) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(32): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(33) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(33): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(34) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(34): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(35) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(35): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(36) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(36): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 36 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(37) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(37): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(38) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(38): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(39) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(39): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(40) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(40): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(41) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(41): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(43) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(43): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 1 passed_lock.v(44) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(44): truncated value with size 5 to match size of target (1)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "try_count passed_lock.v(84) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(84): variable \"try_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 84 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "pass_count passed_lock.v(89) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(89): variable \"pass_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 89 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "alarm_count passed_lock.v(94) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(94): variable \"alarm_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 94 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "passed_lock.v(80) " "Info (10264): Verilog HDL Case Statement information at passed_lock.v(80): all case item expressions in this case statement are onehot" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 80 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 passed_lock.v(145) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(145): truncated value with size 32 to match size of target (11)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 145 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 passed_lock.v(157) " "Warning (10230): Verilog HDL assignment warning at passed_lock.v(157): truncated value with size 32 to match size of target (8)" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "cancel passed_lock.v(186) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(186): variable \"cancel\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 186 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "passed_lock.v(191) " "Warning (10270): Verilog HDL Case Statement warning at passed_lock.v(191): incomplete case statement has no default case item" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 191 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "passed_lock.v(191) " "Info (10264): Verilog HDL Case Statement information at passed_lock.v(191): all case item expressions in this case statement are onehot" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 191 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "enter passed_lock.v(202) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(202): variable \"enter\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 202 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "next_sub_state passed_lock.v(206) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(206): variable \"next_sub_state\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 206 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "next_sub_state passed_lock.v(208) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(208): variable \"next_sub_state\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 208 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "next_sub_state passed_lock.v(210) " "Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(210): variable \"next_sub_state\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 210 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}