lcdfinal.map.qmsg

来自「用状态机实现密码锁State machine used to achieve c」· QMSG 代码 · 共 134 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 31 16:06:47 2009 " "Info: Processing started: Tue Mar 31 16:06:47 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_Controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_Controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Controller " "Info: Found entity 1: LCD_Controller" {  } { { "LCD_Controller.v" "" { Text "F:/jeffie/final/STATE2/LCD_Controller.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "LCD_TEST_initial.v(103) " "Warning (10268): Verilog HDL information at LCD_TEST_initial.v(103): always construct contains both blocking and non-blocking assignments" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST_initial.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST_initial.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_initial " "Info: Found entity 1: LCD_TEST_initial" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcdfinal.v(108) " "Warning (10268): Verilog HDL information at lcdfinal.v(108): always construct contains both blocking and non-blocking assignments" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 108 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "password lcdfinal.v(104) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(104): created implicit net for \"password\"" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 104 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "try_count lcdfinal.v(105) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(105): created implicit net for \"try_count\"" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 105 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "main_state lcdfinal.v(106) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(106): created implicit net for \"main_state\"" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 106 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdfinal.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcdfinal.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcdfinal " "Info: Found entity 1: lcdfinal" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCDmodule.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCDmodule.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCDmodule " "Info: Found entity 1: LCDmodule" {  } { { "LCDmodule.v" "" { Text "F:/jeffie/final/STATE2/LCDmodule.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "password PASSWORD passed_lock.v(20) " "Info (10281): Verilog HDL Declaration information at passed_lock.v(20): object \"password\" differs only in case from object \"PASSWORD\" in the same scope" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "passed_lock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file passed_lock.v" { { "Info" "ISGN_ENTITY_NAME" "1 passed_lock " "Info: Found entity 1: passed_lock" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcdfinal " "Info: Elaborating entity \"lcdfinal\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Reset_Delay.v 1 1 " "Warning: Using design file Reset_Delay.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" {  } { { "Reset_Delay.v" "" { Text "F:/jeffie/final/STATE2/Reset_Delay.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:r0 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:r0\"" {  } { { "lcdfinal.v" "r0" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 43 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 Reset_Delay.v(11) " "Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(11): truncated value with size 32 to match size of target (20)" {  } { { "Reset_Delay.v" "" { Text "F:/jeffie/final/STATE2/Reset_Delay.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "passed_lock passed_lock:p0 " "Info: Elaborating entity \"passed_lock\" for hierarchy \"passed_lock:p0\"" {  } { { "lcdfinal.v" "p0" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 107 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "one passed_lock.v(32) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(32): object \"one\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 32 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "two passed_lock.v(33) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(33): object \"two\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 33 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "three passed_lock.v(34) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(34): object \"three\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 34 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "four passed_lock.v(35) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(35): object \"four\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 35 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "five passed_lock.v(36) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(36): object \"five\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 36 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "six passed_lock.v(37) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(37): object \"six\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 37 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "seven passed_lock.v(38) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(38): object \"seven\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "eight passed_lock.v(39) " "Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(39): object \"eight\" assigned a value but never read" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 39 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}