lcdfinal.hif

用状态机实现密码锁State machine used to achieve code lock

Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
LCD_Controller
# storage
db|lcdfinal.(3).cnf
db|lcdfinal.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCD_Controller.v
a1e9e32719c37c21943c1cc1e81b859
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
CLK_Divide
16
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
LCD_TEST_initial:u0|LCD_Controller:u0
}
# macro_sequence

# end
# entity
Reset_Delay
# storage
db|lcdfinal.(4).cnf
db|lcdfinal.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Reset_Delay.v
21768b2a4956d7b3426fdcbed5f8a2d
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Reset_Delay:r0
}
# macro_sequence

# end
# entity
passed_lock
# storage
db|lcdfinal.(1).cnf
db|lcdfinal.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
passed_lock.v
85314bdd2698a374a6c6a9fe01818ec
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
PASSWORD
0000010011010010
PARAMETER_UNSIGNED_BIN
DEF
waits
001
PARAMETER_UNSIGNED_BIN
DEF
pass
010
PARAMETER_UNSIGNED_BIN
DEF
alarm
100
PARAMETER_UNSIGNED_BIN
DEF
first
000
PARAMETER_UNSIGNED_BIN
DEF
second
001
PARAMETER_UNSIGNED_BIN
DEF
third
010
PARAMETER_UNSIGNED_BIN
DEF
fourth
011
PARAMETER_UNSIGNED_BIN
DEF
finish
100
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
passed_lock:p0
}
# macro_sequence

# end
# entity
LCD_TEST_initial
# storage
db|lcdfinal.(2).cnf
db|lcdfinal.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCD_TEST_initial.v
29fae5226bea7beaaf121dc1da15eb27
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
LCD_INTIAL
0
PARAMETER_SIGNED_DEC
DEF
LCD_LINE1
5
PARAMETER_SIGNED_DEC
DEF
LCD_CH_LINE
21
PARAMETER_SIGNED_DEC
DEF
LCD_LINE2
22
PARAMETER_SIGNED_DEC
DEF
LUT_SIZE
38
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
LCD_TEST_initial:u0
}
# macro_sequence

# end
# entity
lcdfinal
# storage
db|lcdfinal.(0).cnf
db|lcdfinal.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcdfinal.v
7c20e6bc3d7345eb413d765927c6863
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# complete