prev_cmp_lcdfinal.tan.qmsg

用状态机实现密码锁State machine used to achieve code lock

{ "Info" "ITDB_TSU_RESULT" "cmd\[4\] SW\[17\] CLOCK_50 9.300 ns register " "Info: tsu for register \"cmd\[4\]\" (data pin = \"SW\[17\]\", clock pin = \"CLOCK_50\") is 9.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.886 ns + Longest pin register " "Info: + Longest pin to register delay is 11.886 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[17\] 1 PIN PIN_V2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 8; PIN Node = 'SW\[17\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[17] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.028 ns) + CELL(0.416 ns) 7.296 ns Equal11~91 2 COMB LCCOMB_X18_Y18_N2 2 " "Info: 2: + IC(6.028 ns) + CELL(0.416 ns) = 7.296 ns; Loc. = LCCOMB_X18_Y18_N2; Fanout = 2; COMB Node = 'Equal11~91'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.444 ns" { SW[17] Equal11~91 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.495 ns) + CELL(0.438 ns) 8.229 ns Equal12~83 3 COMB LCCOMB_X19_Y18_N22 1 " "Info: 3: + IC(0.495 ns) + CELL(0.438 ns) = 8.229 ns; Loc. = LCCOMB_X19_Y18_N22; Fanout = 1; COMB Node = 'Equal12~83'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { Equal11~91 Equal12~83 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.244 ns) + CELL(0.393 ns) 8.866 ns Equal12~84 4 COMB LCCOMB_X19_Y18_N18 2 " "Info: 4: + IC(0.244 ns) + CELL(0.393 ns) = 8.866 ns; Loc. = LCCOMB_X19_Y18_N18; Fanout = 2; COMB Node = 'Equal12~84'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.637 ns" { Equal12~83 Equal12~84 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.376 ns) 9.685 ns WideOr4~37 5 COMB LCCOMB_X20_Y18_N12 2 " "Info: 5: + IC(0.443 ns) + CELL(0.376 ns) = 9.685 ns; Loc. = LCCOMB_X20_Y18_N12; Fanout = 2; COMB Node = 'WideOr4~37'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.819 ns" { Equal12~84 WideOr4~37 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.275 ns) + CELL(0.438 ns) 10.398 ns WideOr4~38 6 COMB LCCOMB_X20_Y18_N26 2 " "Info: 6: + IC(0.275 ns) + CELL(0.438 ns) = 10.398 ns; Loc. = LCCOMB_X20_Y18_N26; Fanout = 2; COMB Node = 'WideOr4~38'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.713 ns" { WideOr4~37 WideOr4~38 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.245 ns) 11.083 ns WideNor0~45 7 COMB LCCOMB_X20_Y18_N10 1 " "Info: 7: + IC(0.440 ns) + CELL(0.245 ns) = 11.083 ns; Loc. = LCCOMB_X20_Y18_N10; Fanout = 1; COMB Node = 'WideNor0~45'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { WideOr4~38 WideNor0~45 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.366 ns) 11.886 ns cmd\[4\] 8 REG LCFF_X20_Y18_N17 13 " "Info: 8: + IC(0.437 ns) + CELL(0.366 ns) = 11.886 ns; Loc. = LCFF_X20_Y18_N17; Fanout = 13; REG Node = 'cmd\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { WideNor0~45 cmd[4] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.524 ns ( 29.65 % ) " "Info: Total cell delay = 3.524 ns ( 29.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.362 ns ( 70.35 % ) " "Info: Total interconnect delay = 8.362 ns ( 70.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.886 ns" { SW[17] Equal11~91 Equal12~83 Equal12~84 WideOr4~37 WideOr4~38 WideNor0~45 cmd[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.886 ns" { SW[17] {} SW[17]~combout {} Equal11~91 {} Equal12~83 {} Equal12~84 {} WideOr4~37 {} WideOr4~38 {} WideNor0~45 {} cmd[4] {} } { 0.000ns 0.000ns 6.028ns 0.495ns 0.244ns 0.443ns 0.275ns 0.440ns 0.437ns } { 0.000ns 0.852ns 0.416ns 0.438ns 0.393ns 0.376ns 0.438ns 0.245ns 0.366ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.550 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.550 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.550 ns cmd\[4\] 2 REG LCFF_X20_Y18_N17 13 " "Info: 2: + IC(1.014 ns) + CELL(0.537 ns) = 2.550 ns; Loc. = LCFF_X20_Y18_N17; Fanout = 13; REG Node = 'cmd\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { CLOCK_50 cmd[4] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 60.24 % ) " "Info: Total cell delay = 1.536 ns ( 60.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.014 ns ( 39.76 % ) " "Info: Total interconnect delay = 1.014 ns ( 39.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.550 ns" { CLOCK_50 cmd[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.550 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[4] {} } { 0.000ns 0.000ns 1.014ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.886 ns" { SW[17] Equal11~91 Equal12~83 Equal12~84 WideOr4~37 WideOr4~38 WideNor0~45 cmd[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.886 ns" { SW[17] {} SW[17]~combout {} Equal11~91 {} Equal12~83 {} Equal12~84 {} WideOr4~37 {} WideOr4~38 {} WideNor0~45 {} cmd[4] {} } { 0.000ns 0.000ns 6.028ns 0.495ns 0.244ns 0.443ns 0.275ns 0.440ns 0.437ns } { 0.000ns 0.852ns 0.416ns 0.438ns 0.393ns 0.376ns 0.438ns 0.245ns 0.366ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.550 ns" { CLOCK_50 cmd[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.550 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[4] {} } { 0.000ns 0.000ns 1.014ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LCD_RS LCD_TEST_initial:u0\|mLCD_RS 8.585 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LCD_RS\" through register \"LCD_TEST_initial:u0\|mLCD_RS\" is 8.585 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.688 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.537 ns) 2.688 ns LCD_TEST_initial:u0\|mLCD_RS 3 REG LCFF_X24_Y16_N25 1 " "Info: 3: + IC(1.034 ns) + CELL(0.537 ns) = 2.688 ns; Loc. = LCFF_X24_Y16_N25; Fanout = 1; REG Node = 'LCD_TEST_initial:u0\|mLCD_RS'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { CLOCK_50~clkctrl LCD_TEST_initial:u0|mLCD_RS } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.14 % ) " "Info: Total cell delay = 1.536 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.152 ns ( 42.86 % ) " "Info: Total interconnect delay = 1.152 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.688 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_initial:u0|mLCD_RS } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.688 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_initial:u0|mLCD_RS {} } { 0.000ns 0.000ns 0.118ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.647 ns + Longest register pin " "Info: + Longest register to pin delay is 5.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_TEST_initial:u0\|mLCD_RS 1 REG LCFF_X24_Y16_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y16_N25; Fanout = 1; REG Node = 'LCD_TEST_initial:u0\|mLCD_RS'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_TEST_initial:u0|mLCD_RS } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.005 ns) + CELL(2.642 ns) 5.647 ns LCD_RS 2 PIN PIN_K1 0 " "Info: 2: + IC(3.005 ns) + CELL(2.642 ns) = 5.647 ns; Loc. = PIN_K1; Fanout = 0; PIN Node = 'LCD_RS'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.647 ns" { LCD_TEST_initial:u0|mLCD_RS LCD_RS } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 46.79 % ) " "Info: Total cell delay = 2.642 ns ( 46.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.005 ns ( 53.21 % ) " "Info: Total interconnect delay = 3.005 ns ( 53.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.647 ns" { LCD_TEST_initial:u0|mLCD_RS LCD_RS } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.647 ns" { LCD_TEST_initial:u0|mLCD_RS {} LCD_RS {} } { 0.000ns 3.005ns } { 0.000ns 2.642ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.688 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_initial:u0|mLCD_RS } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.688 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_initial:u0|mLCD_RS {} } { 0.000ns 0.000ns 0.118ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.647 ns" { LCD_TEST_initial:u0|mLCD_RS LCD_RS } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.647 ns" { LCD_TEST_initial:u0|mLCD_RS {} LCD_RS {} } { 0.000ns 3.005ns } { 0.000ns 2.642ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "low_sw\[11\] SW\[11\] CLOCK_50 0.685 ns register " "Info: th for register \"low_sw\[11\]\" (data pin = \"SW\[11\]\", clock pin = \"CLOCK_50\") is 0.685 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.682 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 2.682 ns low_sw\[11\] 3 REG LCFF_X17_Y18_N5 2 " "Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X17_Y18_N5; Fanout = 2; REG Node = 'low_sw\[11\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { CLOCK_50~clkctrl low_sw[11] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.27 % ) " "Info: Total cell delay = 1.536 ns ( 57.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 42.73 % ) " "Info: Total interconnect delay = 1.146 ns ( 42.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { CLOCK_50 CLOCK_50~clkctrl low_sw[11] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} low_sw[11] {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.263 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[11\] 1 PIN PIN_P1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 6; PIN Node = 'SW\[11\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[11] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.149 ns) 2.179 ns low_sw\[11\]~feeder 2 COMB LCCOMB_X17_Y18_N4 1 " "Info: 2: + IC(1.031 ns) + CELL(0.149 ns) = 2.179 ns; Loc. = LCCOMB_X17_Y18_N4; Fanout = 1; COMB Node = 'low_sw\[11\]~feeder'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { SW[11] low_sw[11]~feeder } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.263 ns low_sw\[11\] 3 REG LCFF_X17_Y18_N5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.263 ns; Loc. = LCFF_X17_Y18_N5; Fanout = 2; REG Node = 'low_sw\[11\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { low_sw[11]~feeder low_sw[11] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.232 ns ( 54.44 % ) " "Info: Total cell delay = 1.232 ns ( 54.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 45.56 % ) " "Info: Total interconnect delay = 1.031 ns ( 45.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.263 ns" { SW[11] low_sw[11]~feeder low_sw[11] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.263 ns" { SW[11] {} SW[11]~combout {} low_sw[11]~feeder {} low_sw[11] {} } { 0.000ns 0.000ns 1.031ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { CLOCK_50 CLOCK_50~clkctrl low_sw[11] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} low_sw[11] {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.263 ns" { SW[11] low_sw[11]~feeder low_sw[11] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.263 ns" { SW[11] {} SW[11]~combout {} low_sw[11]~feeder {} low_sw[11] {} } { 0.000ns 0.000ns 1.031ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}