lcdfinal.tan.qmsg

用状态机实现密码锁State machine used to achieve code lock

{ "Info" "ITDB_TSU_RESULT" "cmd\[1\] SW\[16\] CLOCK_50 7.944 ns register " "Info: tsu for register \"cmd\[1\]\" (data pin = \"SW\[16\]\", clock pin = \"CLOCK_50\") is 7.944 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.652 ns + Longest pin register " "Info: + Longest pin to register delay is 10.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[16\] 1 PIN PIN_V1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V1; Fanout = 4; PIN Node = 'SW\[16\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[16] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.209 ns) + CELL(0.275 ns) 7.336 ns Equal3~120 2 COMB LCCOMB_X36_Y20_N20 3 " "Info: 2: + IC(6.209 ns) + CELL(0.275 ns) = 7.336 ns; Loc. = LCCOMB_X36_Y20_N20; Fanout = 3; COMB Node = 'Equal3~120'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.484 ns" { SW[16] Equal3~120 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.406 ns) 8.016 ns Equal1~81 3 COMB LCCOMB_X36_Y20_N26 6 " "Info: 3: + IC(0.274 ns) + CELL(0.406 ns) = 8.016 ns; Loc. = LCCOMB_X36_Y20_N26; Fanout = 6; COMB Node = 'Equal1~81'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.680 ns" { Equal3~120 Equal1~81 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.393 ns) 9.159 ns Equal12~83 4 COMB LCCOMB_X37_Y21_N10 2 " "Info: 4: + IC(0.750 ns) + CELL(0.393 ns) = 9.159 ns; Loc. = LCCOMB_X37_Y21_N10; Fanout = 2; COMB Node = 'Equal12~83'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.143 ns" { Equal1~81 Equal12~83 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.280 ns) + CELL(0.398 ns) 9.837 ns WideOr4~36 5 COMB LCCOMB_X37_Y21_N28 2 " "Info: 5: + IC(0.280 ns) + CELL(0.398 ns) = 9.837 ns; Loc. = LCCOMB_X37_Y21_N28; Fanout = 2; COMB Node = 'WideOr4~36'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.678 ns" { Equal12~83 WideOr4~36 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.275 ns) 10.568 ns WideOr3~1 6 COMB LCCOMB_X37_Y21_N18 1 " "Info: 6: + IC(0.456 ns) + CELL(0.275 ns) = 10.568 ns; Loc. = LCCOMB_X37_Y21_N18; Fanout = 1; COMB Node = 'WideOr3~1'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.731 ns" { WideOr4~36 WideOr3~1 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 10.652 ns cmd\[1\] 7 REG LCFF_X37_Y21_N19 7 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 10.652 ns; Loc. = LCFF_X37_Y21_N19; Fanout = 7; REG Node = 'cmd\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { WideOr3~1 cmd[1] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.683 ns ( 25.19 % ) " "Info: Total cell delay = 2.683 ns ( 25.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.969 ns ( 74.81 % ) " "Info: Total interconnect delay = 7.969 ns ( 74.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.652 ns" { SW[16] Equal3~120 Equal1~81 Equal12~83 WideOr4~36 WideOr3~1 cmd[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.652 ns" { SW[16] {} SW[16]~combout {} Equal3~120 {} Equal1~81 {} Equal12~83 {} WideOr4~36 {} WideOr3~1 {} cmd[1] {} } { 0.000ns 0.000ns 6.209ns 0.274ns 0.750ns 0.280ns 0.456ns 0.000ns } { 0.000ns 0.852ns 0.275ns 0.406ns 0.393ns 0.398ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.672 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 2.672 ns cmd\[1\] 3 REG LCFF_X37_Y21_N19 7 " "Info: 3: + IC(1.018 ns) + CELL(0.537 ns) = 2.672 ns; Loc. = LCFF_X37_Y21_N19; Fanout = 7; REG Node = 'cmd\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { CLOCK_50~clkctrl cmd[1] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.49 % ) " "Info: Total cell delay = 1.536 ns ( 57.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.136 ns ( 42.51 % ) " "Info: Total interconnect delay = 1.136 ns ( 42.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl cmd[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} cmd[1] {} } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.652 ns" { SW[16] Equal3~120 Equal1~81 Equal12~83 WideOr4~36 WideOr3~1 cmd[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.652 ns" { SW[16] {} SW[16]~combout {} Equal3~120 {} Equal1~81 {} Equal12~83 {} WideOr4~36 {} WideOr3~1 {} cmd[1] {} } { 0.000ns 0.000ns 6.209ns 0.274ns 0.750ns 0.280ns 0.456ns 0.000ns } { 0.000ns 0.852ns 0.275ns 0.406ns 0.393ns 0.398ns 0.275ns 0.084ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl cmd[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} cmd[1] {} } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LEDR\[15\] cmd\[2\] 9.657 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LEDR\[15\]\" through register \"cmd\[2\]\" is 9.657 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 3.100 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.537 ns) 3.100 ns cmd\[2\] 2 REG LCFF_X37_Y21_N21 9 " "Info: 2: + IC(1.564 ns) + CELL(0.537 ns) = 3.100 ns; Loc. = LCFF_X37_Y21_N21; Fanout = 9; REG Node = 'cmd\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.101 ns" { CLOCK_50 cmd[2] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 49.55 % ) " "Info: Total cell delay = 1.536 ns ( 49.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 50.45 % ) " "Info: Total interconnect delay = 1.564 ns ( 50.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { CLOCK_50 cmd[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.307 ns + Longest register pin " "Info: + Longest register to pin delay is 6.307 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cmd\[2\] 1 REG LCFF_X37_Y21_N21 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y21_N21; Fanout = 9; REG Node = 'cmd\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { cmd[2] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(2.798 ns) 6.307 ns LEDR\[15\] 2 PIN PIN_AE13 0 " "Info: 2: + IC(3.509 ns) + CELL(2.798 ns) = 6.307 ns; Loc. = PIN_AE13; Fanout = 0; PIN Node = 'LEDR\[15\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.307 ns" { cmd[2] LEDR[15] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 44.36 % ) " "Info: Total cell delay = 2.798 ns ( 44.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.509 ns ( 55.64 % ) " "Info: Total interconnect delay = 3.509 ns ( 55.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.307 ns" { cmd[2] LEDR[15] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.307 ns" { cmd[2] {} LEDR[15] {} } { 0.000ns 3.509ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { CLOCK_50 cmd[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.999ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.307 ns" { cmd[2] LEDR[15] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.307 ns" { cmd[2] {} LEDR[15] {} } { 0.000ns 3.509ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "low_sw\[7\] SW\[7\] CLOCK_50 0.522 ns register " "Info: th for register \"low_sw\[7\]\" (data pin = \"SW\[7\]\", clock pin = \"CLOCK_50\") is 0.522 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.670 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.537 ns) 2.670 ns low_sw\[7\] 3 REG LCFF_X36_Y20_N1 2 " "Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X36_Y20_N1; Fanout = 2; REG Node = 'low_sw\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { CLOCK_50~clkctrl low_sw[7] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.53 % ) " "Info: Total cell delay = 1.536 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.134 ns ( 42.47 % ) " "Info: Total interconnect delay = 1.134 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { CLOCK_50 CLOCK_50~clkctrl low_sw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} low_sw[7] {} } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.414 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns SW\[7\] 1 PIN PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'SW\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.149 ns) 2.330 ns low_sw\[7\]~feeder 2 COMB LCCOMB_X36_Y20_N0 1 " "Info: 2: + IC(1.202 ns) + CELL(0.149 ns) = 2.330 ns; Loc. = LCCOMB_X36_Y20_N0; Fanout = 1; COMB Node = 'low_sw\[7\]~feeder'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.351 ns" { SW[7] low_sw[7]~feeder } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.414 ns low_sw\[7\] 3 REG LCFF_X36_Y20_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.414 ns; Loc. = LCFF_X36_Y20_N1; Fanout = 2; REG Node = 'low_sw\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { low_sw[7]~feeder low_sw[7] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.212 ns ( 50.21 % ) " "Info: Total cell delay = 1.212 ns ( 50.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.202 ns ( 49.79 % ) " "Info: Total interconnect delay = 1.202 ns ( 49.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.414 ns" { SW[7] low_sw[7]~feeder low_sw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.414 ns" { SW[7] {} SW[7]~combout {} low_sw[7]~feeder {} low_sw[7] {} } { 0.000ns 0.000ns 1.202ns 0.000ns } { 0.000ns 0.979ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { CLOCK_50 CLOCK_50~clkctrl low_sw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} low_sw[7] {} } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.414 ns" { SW[7] low_sw[7]~feeder low_sw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.414 ns" { SW[7] {} SW[7]~combout {} low_sw[7]~feeder {} low_sw[7] {} } { 0.000ns 0.000ns 1.202ns 0.000ns } { 0.000ns 0.979ns 0.149ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}