lcdfinal.tan.qmsg

用状态机实现密码锁State machine used to achieve code lock

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register passed_lock:p0\|next_sub_state.first_633 register passed_lock:p0\|sub_state.first 94.73 MHz 10.556 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 94.73 MHz between source register \"passed_lock:p0\|next_sub_state.first_633\" and destination register \"passed_lock:p0\|sub_state.first\" (period= 10.556 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.486 ns + Longest register register " "Info: + Longest register to register delay is 0.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns passed_lock:p0\|next_sub_state.first_633 1 REG LCCOMB_X36_Y21_N30 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X36_Y21_N30; Fanout = 1; REG Node = 'passed_lock:p0\|next_sub_state.first_633'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.252 ns) + CELL(0.150 ns) 0.402 ns passed_lock:p0\|sub_state.first~8 2 COMB LCCOMB_X36_Y21_N18 1 " "Info: 2: + IC(0.252 ns) + CELL(0.150 ns) = 0.402 ns; Loc. = LCCOMB_X36_Y21_N18; Fanout = 1; COMB Node = 'passed_lock:p0\|sub_state.first~8'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.402 ns" { passed_lock:p0|next_sub_state.first_633 passed_lock:p0|sub_state.first~8 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.486 ns passed_lock:p0\|sub_state.first 3 REG LCFF_X36_Y21_N19 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.486 ns; Loc. = LCFF_X36_Y21_N19; Fanout = 4; REG Node = 'passed_lock:p0\|sub_state.first'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { passed_lock:p0|sub_state.first~8 passed_lock:p0|sub_state.first } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 48.15 % ) " "Info: Total cell delay = 0.234 ns ( 48.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.252 ns ( 51.85 % ) " "Info: Total interconnect delay = 0.252 ns ( 51.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.486 ns" { passed_lock:p0|next_sub_state.first_633 passed_lock:p0|sub_state.first~8 passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.486 ns" { passed_lock:p0|next_sub_state.first_633 {} passed_lock:p0|sub_state.first~8 {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.252ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.828 ns - Smallest " "Info: - Smallest clock skew is -4.828 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.668 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 2.668 ns passed_lock:p0\|sub_state.first 3 REG LCFF_X36_Y21_N19 4 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X36_Y21_N19; Fanout = 4; REG Node = 'passed_lock:p0\|sub_state.first'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.57 % ) " "Info: Total cell delay = 1.536 ns ( 57.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.132 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.132 ns ( 42.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 7.496 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 7.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.787 ns) 3.350 ns cmd\[4\] 2 REG LCFF_X37_Y21_N17 14 " "Info: 2: + IC(1.564 ns) + CELL(0.787 ns) = 3.350 ns; Loc. = LCFF_X37_Y21_N17; Fanout = 14; REG Node = 'cmd\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.351 ns" { CLOCK_50 cmd[4] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.607 ns) + CELL(0.438 ns) 4.395 ns passed_lock:p0\|next_sub_state.finish~2 3 COMB LCCOMB_X36_Y21_N0 1 " "Info: 3: + IC(0.607 ns) + CELL(0.438 ns) = 4.395 ns; Loc. = LCCOMB_X36_Y21_N0; Fanout = 1; COMB Node = 'passed_lock:p0\|next_sub_state.finish~2'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.045 ns" { cmd[4] passed_lock:p0|next_sub_state.finish~2 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(0.000 ns) 6.028 ns passed_lock:p0\|next_sub_state.finish~2clkctrl 4 COMB CLKCTRL_G11 5 " "Info: 4: + IC(1.633 ns) + CELL(0.000 ns) = 6.028 ns; Loc. = CLKCTRL_G11; Fanout = 5; COMB Node = 'passed_lock:p0\|next_sub_state.finish~2clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.633 ns" { passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.318 ns) + CELL(0.150 ns) 7.496 ns passed_lock:p0\|next_sub_state.first_633 5 REG LCCOMB_X36_Y21_N30 1 " "Info: 5: + IC(1.318 ns) + CELL(0.150 ns) = 7.496 ns; Loc. = LCCOMB_X36_Y21_N30; Fanout = 1; REG Node = 'passed_lock:p0\|next_sub_state.first_633'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.468 ns" { passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.374 ns ( 31.67 % ) " "Info: Total cell delay = 2.374 ns ( 31.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.122 ns ( 68.33 % ) " "Info: Total interconnect delay = 5.122 ns ( 68.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.496 ns" { CLOCK_50 cmd[4] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.496 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[4] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.564ns 0.607ns 1.633ns 1.318ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.496 ns" { CLOCK_50 cmd[4] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.496 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[4] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.564ns 0.607ns 1.633ns 1.318ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.486 ns" { passed_lock:p0|next_sub_state.first_633 passed_lock:p0|sub_state.first~8 passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.486 ns" { passed_lock:p0|next_sub_state.first_633 {} passed_lock:p0|sub_state.first~8 {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.252ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.496 ns" { CLOCK_50 cmd[4] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.496 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[4] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.564ns 0.607ns 1.633ns 1.318ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLOCK_50 107 " "Warning: Circuit may not operate. Detected 107 non-operational path(s) clocked by clock \"CLOCK_50\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "LCD_TEST_initial:u0\|LUT_INDEX\[3\] LCD_TEST_initial:u0\|LUT_DATA\[7\] CLOCK_50 3.455 ns " "Info: Found hold time violation between source  pin or register \"LCD_TEST_initial:u0\|LUT_INDEX\[3\]\" and destination pin or register \"LCD_TEST_initial:u0\|LUT_DATA\[7\]\" for clock \"CLOCK_50\" (Hold time is 3.455 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.708 ns + Largest " "Info: + Largest clock skew is 4.708 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 7.389 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 7.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.640 ns) + CELL(0.787 ns) 3.426 ns LCD_XX\[4\] 2 REG LCFF_X27_Y24_N17 3 " "Info: 2: + IC(1.640 ns) + CELL(0.787 ns) = 3.426 ns; Loc. = LCFF_X27_Y24_N17; Fanout = 3; REG Node = 'LCD_XX\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.427 ns" { CLOCK_50 LCD_XX[4] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.438 ns) 4.214 ns LCD_TEST_initial:u0\|WideOr23~85 3 COMB LCCOMB_X27_Y24_N20 1 " "Info: 3: + IC(0.350 ns) + CELL(0.438 ns) = 4.214 ns; Loc. = LCCOMB_X27_Y24_N20; Fanout = 1; COMB Node = 'LCD_TEST_initial:u0\|WideOr23~85'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.788 ns" { LCD_XX[4] LCD_TEST_initial:u0|WideOr23~85 } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.682 ns) + CELL(0.000 ns) 5.896 ns LCD_TEST_initial:u0\|WideOr23~85clkctrl 4 COMB CLKCTRL_G8 9 " "Info: 4: + IC(1.682 ns) + CELL(0.000 ns) = 5.896 ns; Loc. = CLKCTRL_G8; Fanout = 9; COMB Node = 'LCD_TEST_initial:u0\|WideOr23~85clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.682 ns" { LCD_TEST_initial:u0|WideOr23~85 LCD_TEST_initial:u0|WideOr23~85clkctrl } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.343 ns) + CELL(0.150 ns) 7.389 ns LCD_TEST_initial:u0\|LUT_DATA\[7\] 5 REG LCCOMB_X28_Y24_N18 1 " "Info: 5: + IC(1.343 ns) + CELL(0.150 ns) = 7.389 ns; Loc. = LCCOMB_X28_Y24_N18; Fanout = 1; REG Node = 'LCD_TEST_initial:u0\|LUT_DATA\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { LCD_TEST_initial:u0|WideOr23~85clkctrl LCD_TEST_initial:u0|LUT_DATA[7] } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.374 ns ( 32.13 % ) " "Info: Total cell delay = 2.374 ns ( 32.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.015 ns ( 67.87 % ) " "Info: Total interconnect delay = 5.015 ns ( 67.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.389 ns" { CLOCK_50 LCD_XX[4] LCD_TEST_initial:u0|WideOr23~85 LCD_TEST_initial:u0|WideOr23~85clkctrl LCD_TEST_initial:u0|LUT_DATA[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.389 ns" { CLOCK_50 {} CLOCK_50~combout {} LCD_XX[4] {} LCD_TEST_initial:u0|WideOr23~85 {} LCD_TEST_initial:u0|WideOr23~85clkctrl {} LCD_TEST_initial:u0|LUT_DATA[7] {} } { 0.000ns 0.000ns 1.640ns 0.350ns 1.682ns 1.343ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.681 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to source register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.681 ns LCD_TEST_initial:u0\|LUT_INDEX\[3\] 3 REG LCFF_X28_Y24_N27 37 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X28_Y24_N27; Fanout = 37; REG Node = 'LCD_TEST_initial:u0\|LUT_INDEX\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { CLOCK_50~clkctrl LCD_TEST_initial:u0|LUT_INDEX[3] } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.29 % ) " "Info: Total cell delay = 1.536 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.145 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_initial:u0|LUT_INDEX[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_initial:u0|LUT_INDEX[3] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.389 ns" { CLOCK_50 LCD_XX[4] LCD_TEST_initial:u0|WideOr23~85 LCD_TEST_initial:u0|WideOr23~85clkctrl LCD_TEST_initial:u0|LUT_DATA[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.389 ns" { CLOCK_50 {} CLOCK_50~combout {} LCD_XX[4] {} LCD_TEST_initial:u0|WideOr23~85 {} LCD_TEST_initial:u0|WideOr23~85clkctrl {} LCD_TEST_initial:u0|LUT_DATA[7] {} } { 0.000ns 0.000ns 1.640ns 0.350ns 1.682ns 1.343ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_initial:u0|LUT_INDEX[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_initial:u0|LUT_INDEX[3] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 98 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.003 ns - Shortest register register " "Info: - Shortest register to register delay is 1.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_TEST_initial:u0\|LUT_INDEX\[3\] 1 REG LCFF_X28_Y24_N27 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y24_N27; Fanout = 37; REG Node = 'LCD_TEST_initial:u0\|LUT_INDEX\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_TEST_initial:u0|LUT_INDEX[3] } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.333 ns) + CELL(0.150 ns) 0.483 ns LCD_TEST_initial:u0\|LUT_DATA~163 2 COMB LCCOMB_X28_Y24_N20 1 " "Info: 2: + IC(0.333 ns) + CELL(0.150 ns) = 0.483 ns; Loc. = LCCOMB_X28_Y24_N20; Fanout = 1; COMB Node = 'LCD_TEST_initial:u0\|LUT_DATA~163'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.483 ns" { LCD_TEST_initial:u0|LUT_INDEX[3] LCD_TEST_initial:u0|LUT_DATA~163 } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.271 ns) 1.003 ns LCD_TEST_initial:u0\|LUT_DATA\[7\] 3 REG LCCOMB_X28_Y24_N18 1 " "Info: 3: + IC(0.249 ns) + CELL(0.271 ns) = 1.003 ns; Loc. = LCCOMB_X28_Y24_N18; Fanout = 1; REG Node = 'LCD_TEST_initial:u0\|LUT_DATA\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.520 ns" { LCD_TEST_initial:u0|LUT_DATA~163 LCD_TEST_initial:u0|LUT_DATA[7] } "NODE_NAME" } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.421 ns ( 41.97 % ) " "Info: Total cell delay = 0.421 ns ( 41.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.582 ns ( 58.03 % ) " "Info: Total interconnect delay = 0.582 ns ( 58.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.003 ns" { LCD_TEST_initial:u0|LUT_INDEX[3] LCD_TEST_initial:u0|LUT_DATA~163 LCD_TEST_initial:u0|LUT_DATA[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.003 ns" { LCD_TEST_initial:u0|LUT_INDEX[3] {} LCD_TEST_initial:u0|LUT_DATA~163 {} LCD_TEST_initial:u0|LUT_DATA[7] {} } { 0.000ns 0.333ns 0.249ns } { 0.000ns 0.150ns 0.271ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 98 -1 0 } } { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.389 ns" { CLOCK_50 LCD_XX[4] LCD_TEST_initial:u0|WideOr23~85 LCD_TEST_initial:u0|WideOr23~85clkctrl LCD_TEST_initial:u0|LUT_DATA[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.389 ns" { CLOCK_50 {} CLOCK_50~combout {} LCD_XX[4] {} LCD_TEST_initial:u0|WideOr23~85 {} LCD_TEST_initial:u0|WideOr23~85clkctrl {} LCD_TEST_initial:u0|LUT_DATA[7] {} } { 0.000ns 0.000ns 1.640ns 0.350ns 1.682ns 1.343ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_initial:u0|LUT_INDEX[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_initial:u0|LUT_INDEX[3] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.003 ns" { LCD_TEST_initial:u0|LUT_INDEX[3] LCD_TEST_initial:u0|LUT_DATA~163 LCD_TEST_initial:u0|LUT_DATA[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.003 ns" { LCD_TEST_initial:u0|LUT_INDEX[3] {} LCD_TEST_initial:u0|LUT_DATA~163 {} LCD_TEST_initial:u0|LUT_DATA[7] {} } { 0.000ns 0.333ns 0.249ns } { 0.000ns 0.150ns 0.271ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}