prev_cmp_lcdfinal.qmsg

用状态机实现密码锁State machine used to achieve code lock

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 31 16:06:00 2009 " "Info: Processing started: Tue Mar 31 16:06:00 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_Controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_Controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Controller " "Info: Found entity 1: LCD_Controller" {  } { { "LCD_Controller.v" "" { Text "F:/jeffie/final/STATE2/LCD_Controller.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "LCD_TEST_initial.v(103) " "Warning (10268): Verilog HDL information at LCD_TEST_initial.v(103): always construct contains both blocking and non-blocking assignments" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 103 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST_initial.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST_initial.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_initial " "Info: Found entity 1: LCD_TEST_initial" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/STATE2/LCD_TEST_initial.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcdfinal.v(108) " "Warning (10268): Verilog HDL information at lcdfinal.v(108): always construct contains both blocking and non-blocking assignments" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 108 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "password lcdfinal.v(104) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(104): created implicit net for \"password\"" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 104 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "try_count lcdfinal.v(105) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(105): created implicit net for \"try_count\"" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 105 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "main_state lcdfinal.v(106) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(106): created implicit net for \"main_state\"" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 106 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdfinal.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcdfinal.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcdfinal " "Info: Found entity 1: lcdfinal" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCDmodule.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCDmodule.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCDmodule " "Info: Found entity 1: LCDmodule" {  } { { "LCDmodule.v" "" { Text "F:/jeffie/final/STATE2/LCDmodule.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "password PASSWORD passed_lock.v(20) " "Info (10281): Verilog HDL Declaration information at passed_lock.v(20): object \"password\" differs only in case from object \"PASSWORD\" in the same scope" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "passed_lock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file passed_lock.v" { { "Info" "ISGN_ENTITY_NAME" "1 passed_lock " "Info: Found entity 1: passed_lock" {  } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_SV_NO_SINGLE_VALUED_PACKED_DIMENSION" "lcdfinal.v(24) " "Error (10989): SystemVerilog error at lcdfinal.v(24): can't declare packed array dimension with a single-valued range" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 24 0 0 } }  } 0 10989 "SystemVerilog error at %1!s!: can't declare packed array dimension with a single-valued range" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/jeffie/final/STATE2/lcdfinal.map.smsg " "Info: Generated suppressed messages file F:/jeffie/final/STATE2/lcdfinal.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  3 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Error: Peak virtual memory: 160 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 31 16:06:02 2009 " "Error: Processing ended: Tue Mar 31 16:06:02 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 3 s " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 3 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}