lcdfinal.map.rpt

用状态机实现密码锁State machine used to achieve code lock

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |lcdfinal|LCD_TEST_initial:u0|LUT_INDEX[0]             ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |lcdfinal|passed_lock:p0|try_count[0]                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |lcdfinal|LCD_TEST_initial:u0|LCD_Controller:u0|mStart ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |lcdfinal|LCD_TEST_initial:u0|mLCD_ST~16               ;
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |lcdfinal|LCD_TEST_initial:u0|Selector12               ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; No         ; |lcdfinal|passed_lock:p0|next_sub_state.third~2        ;
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; No         ; |lcdfinal|LCD_TEST_initial:u0|mLCD_ST~14               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------+


+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: passed_lock:p0 ;
+----------------+------------------+-------------------------+
; Parameter Name ; Value            ; Type                    ;
+----------------+------------------+-------------------------+
; PASSWORD       ; 0000010011010010 ; Unsigned Binary         ;
; waits          ; 001              ; Unsigned Binary         ;
; pass           ; 010              ; Unsigned Binary         ;
; alarm          ; 100              ; Unsigned Binary         ;
; first          ; 000              ; Unsigned Binary         ;
; second         ; 001              ; Unsigned Binary         ;
; third          ; 010              ; Unsigned Binary         ;
; fourth         ; 011              ; Unsigned Binary         ;
; finish         ; 100              ; Unsigned Binary         ;
+----------------+------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LCD_TEST_initial:u0 ;
+----------------+-------+-----------------------------------------+
; Parameter Name ; Value ; Type                                    ;
+----------------+-------+-----------------------------------------+
; LCD_INTIAL     ; 0     ; Signed Integer                          ;
; LCD_LINE1      ; 5     ; Signed Integer                          ;
; LCD_CH_LINE    ; 21    ; Signed Integer                          ;
; LCD_LINE2      ; 22    ; Signed Integer                          ;
; LUT_SIZE       ; 38    ; Signed Integer                          ;
+----------------+-------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LCD_TEST_initial:u0|LCD_Controller:u0 ;
+----------------+-------+-----------------------------------------------------------+
; Parameter Name ; Value ; Type                                                      ;
+----------------+-------+-----------------------------------------------------------+
; CLK_Divide     ; 16    ; Signed Integer                                            ;
+----------------+-------+-----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Mar 31 16:06:47 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal
Info: Found 1 design units, including 1 entities, in source file LCD_Controller.v
    Info: Found entity 1: LCD_Controller
Info: Found 1 design units, including 1 entities, in source file LCD_TEST_initial.v
    Info: Found entity 1: LCD_TEST_initial
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(104): created implicit net for "password"
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(105): created implicit net for "try_count"
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal.v(106): created implicit net for "main_state"
Info: Found 1 design units, including 1 entities, in source file lcdfinal.v
    Info: Found entity 1: lcdfinal
Info: Found 1 design units, including 1 entities, in source file LCDmodule.v
    Info: Found entity 1: LCDmodule
Info: Found 1 design units, including 1 entities, in source file passed_lock.v
    Info: Found entity 1: passed_lock
Info: Elaborating entity "lcdfinal" for the top level hierarchy
Warning: Using design file Reset_Delay.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Reset_Delay
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:r0"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(11): truncated value with size 32 to match size of target (20)
Info: Elaborating entity "passed_lock" for hierarchy "passed_lock:p0"
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(32): object "one" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(33): object "two" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(34): object "three" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(35): object "four" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(36): object "five" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(37): object "six" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(38): object "seven" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(39): object "eight" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(40): object "nine" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at passed_lock.v(41): object "zero" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at passed_lock.v(32): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(33): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(34): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(35): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(36): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(37): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(38): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(39): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(40): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(41): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(43): truncated value with size 5 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(44): truncated value with size 5 to match size of target (1)
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(84): variable "try_count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(89): variable "pass_count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(94): variable "alarm_count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info (10264): Verilog HDL Case Statement information at passed_lock.v(80): all case item expressions in this case statement are onehot
Warning (10230): Verilog HDL assignment warning at passed_lock.v(145): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at passed_lock.v(157): truncated value with size 32 to match size of target (8)
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(186): variable "cancel" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10270): Verilog HDL Case Statement warning at passed_lock.v(191): incomplete case statement has no default case item
Info (10264): Verilog HDL Case Statement information at passed_lock.v(191): all case item expressions in this case statement are onehot
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(202): variable "enter" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(206): variable "next_sub_state" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(208): variable "next_sub_state" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(210): variable "next_sub_state" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at passed_lock.v(212): variable "next_sub_state" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at passed_lock.v(181): inferring latch(es) for variable "next_sub_state", which holds its previous value in one or more paths through the always construct
Info (10264): Verilog HDL Case Statement information at passed_lock.v(267): all case item expressions in this case statement are onehot
Warning (10230): Verilog HDL assignment warning at passed_lock.v(289): truncated value with size 32 to match size of target (2)
Info (10041): Inferred latch for "next_sub_state.finish" at passed_lock.v(232)
Info (10041): Inferred latch for "next_sub_state.fourth" at passed_lock.v(232)
Info (10041): Inferred latch for "next_sub_state.third" at passed_lock.v(232)
Info (10041): Inferred latch for "next_sub_state.second" at passed_lock.v(232)
Info (10041): Inferred latch for "next_sub_state.first" at passed_lock.v(232)
Info: Elaborating entity "LCD_TEST_initial" for hierarchy "LCD_TEST_initial:u0"
Warning (10230): Verilog HDL assignment warning at LCD_TEST_initial.v(75): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at LCD_TEST_initial.v(83): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at LCD_TEST_initial.v(93): truncated value with size 32 to match size of target (6)
Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(105): variable "LCD_XX" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(161): variable "password" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(162): variable "password" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(163): variable "password" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(164): variable "password" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at LCD_TEST_initial.v(175): variable "try_count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10270): Verilog HDL Case Statement warning at LCD_TEST_initial.v(105): incomplete case statement has no default case item
Info (10264): Verilog HDL Case Statement information at LCD_TEST_initial.v(105): all case item expressions in this case statement are onehot
Warning (10240): Verilog HDL Always Construct warning at LCD_TEST_initial.v(103): inferring latch(es) for variable "LEDG", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at LCD_TEST_initial.v(103): inferring latch(es) for variable "LUT_DATA", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at LCD_TEST_initial.v(103): inferring latch(es) for variable "LEDR", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "LEDR[0]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[1]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[2]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[3]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[4]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[5]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[6]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[7]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[8]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[9]" at LCD_TEST_initial.v(103)
Info (10041): Inferred latch for "LEDR[10]" at LCD_TEST_initial.v(103)