lcdfinal.tan.rpt

用状态机实现密码锁State machine used to achieve code lock

; Device Name                                                         ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                     ; To                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 94.73 MHz ( period = 10.556 ns )                    ; passed_lock:p0|next_sub_state.first_633  ; passed_lock:p0|sub_state.first     ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.486 ns                ;
; N/A                                     ; 101.79 MHz ( period = 9.824 ns )                    ; passed_lock:p0|next_sub_state.fourth_585 ; passed_lock:p0|sub_state.fourth    ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 101.81 MHz ( period = 9.822 ns )                    ; passed_lock:p0|next_sub_state.second_617 ; passed_lock:p0|sub_state.second    ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 101.83 MHz ( period = 9.820 ns )                    ; passed_lock:p0|next_sub_state.third_601  ; passed_lock:p0|sub_state.third     ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 102.52 MHz ( period = 9.754 ns )                    ; passed_lock:p0|next_sub_state.finish_569 ; passed_lock:p0|sub_state.finish    ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 104.91 MHz ( period = 9.532 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[6]          ; LCD_TEST_initial:u0|mLCD_DATA[6]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 104.93 MHz ( period = 9.530 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[2]          ; LCD_TEST_initial:u0|mLCD_DATA[2]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 104.93 MHz ( period = 9.530 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[3]          ; LCD_TEST_initial:u0|mLCD_DATA[3]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 105.09 MHz ( period = 9.516 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[0]          ; LCD_TEST_initial:u0|mLCD_DATA[0]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 105.13 MHz ( period = 9.512 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[5]          ; LCD_TEST_initial:u0|mLCD_DATA[5]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 105.13 MHz ( period = 9.512 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[7]          ; LCD_TEST_initial:u0|mLCD_DATA[7]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 105.20 MHz ( period = 9.506 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[8]          ; LCD_TEST_initial:u0|mLCD_RS        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 105.37 MHz ( period = 9.490 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[1]          ; LCD_TEST_initial:u0|mLCD_DATA[1]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 105.37 MHz ( period = 9.490 ns )                    ; LCD_TEST_initial:u0|LUT_DATA[4]          ; LCD_TEST_initial:u0|mLCD_DATA[4]   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.084 ns                ;
; N/A                                     ; 181.62 MHz ( period = 5.506 ns )                    ; low_sw[1]                                ; cmd[0]                             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.294 ns                ;
; N/A                                     ; 181.62 MHz ( period = 5.506 ns )                    ; low_sw[1]                                ; cmd[1]                             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.294 ns                ;
; N/A                                     ; 181.79 MHz ( period = 5.501 ns )                    ; low_sw_r[4]                              ; cmd[0]                             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.289 ns                ;
; N/A                                     ; 181.79 MHz ( period = 5.501 ns )                    ; low_sw_r[4]                              ; cmd[1]                             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.289 ns                ;
; N/A                                     ; 190.55 MHz ( period = 5.248 ns )                    ; low_sw[3]                                ; cmd[0]                             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.036 ns                ;