reset_delay.v

来自「用状态机实现密码锁State machine used to achieve c」· Verilog 代码 · 共 18 行

module	Reset_Delay(iCLK,oRESET);	//复位脉冲只在开始时出现一次
input		iCLK;
output reg	oRESET;
reg	[19:0]	Cont=0;

always@(posedge iCLK)
begin
	if(Cont!=20'hFFFFF)			//分频
	//if(Cont!=20'hFF)
	begin
		Cont	<=	Cont+1;
		oRESET	<=	1'b0;
	end
	else
	oRESET	<=	1'b1;
end

endmodule