uart_hier_info

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

dataa[0] => comptree:comp.dataa[0]
dataa[1] => comptree:comp.dataa[1]
dataa[2] => comptree:comp.dataa[2]
dataa[3] => comptree:comp.dataa[3]
dataa[4] => comptree:comp.dataa[4]
dataa[5] => comptree:comp.dataa[5]
dataa[6] => comptree:comp.dataa[6]
dataa[7] => comptree:comp.dataa[7]
dataa[8] => comptree:comp.dataa[8]
dataa[9] => comptree:comp.dataa[9]
dataa[10] => comptree:comp.dataa[10]
dataa[11] => comptree:comp.dataa[11]
dataa[12] => comptree:comp.dataa[12]
dataa[13] => comptree:comp.dataa[13]
dataa[14] => comptree:comp.dataa[14]
dataa[15] => comptree:comp.dataa[15]
datab[0] => comptree:comp.datab[0]
datab[1] => comptree:comp.datab[1]
datab[2] => comptree:comp.datab[2]
datab[3] => comptree:comp.datab[3]
datab[4] => comptree:comp.datab[4]
datab[5] => comptree:comp.datab[5]
datab[6] => comptree:comp.datab[6]
datab[7] => comptree:comp.datab[7]
datab[8] => comptree:comp.datab[8]
datab[9] => comptree:comp.datab[9]
datab[10] => comptree:comp.datab[10]
datab[11] => comptree:comp.datab[11]
datab[12] => comptree:comp.datab[12]
datab[13] => comptree:comp.datab[13]
datab[14] => comptree:comp.datab[14]
datab[15] => comptree:comp.datab[15]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp
dataa[0] => cmpchain:cmp[0].dataa[0]
dataa[1] => cmpchain:cmp[0].dataa[1]
dataa[2] => cmpchain:cmp[1].dataa[0]
dataa[3] => cmpchain:cmp[1].dataa[1]
dataa[4] => cmpchain:cmp[2].dataa[0]
dataa[5] => cmpchain:cmp[2].dataa[1]
dataa[6] => cmpchain:cmp[3].dataa[0]
dataa[7] => cmpchain:cmp[3].dataa[1]
dataa[8] => cmpchain:cmp[4].dataa[0]
dataa[9] => cmpchain:cmp[4].dataa[1]
dataa[10] => cmpchain:cmp[5].dataa[0]
dataa[11] => cmpchain:cmp[5].dataa[1]
dataa[12] => cmpchain:cmp[6].dataa[0]
dataa[13] => cmpchain:cmp[6].dataa[1]
dataa[14] => cmpchain:cmp[7].dataa[0]
dataa[15] => cmpchain:cmp[7].dataa[1]
datab[0] => cmpchain:cmp[0].datab[0]
datab[1] => cmpchain:cmp[0].datab[1]
datab[2] => cmpchain:cmp[1].datab[0]
datab[3] => cmpchain:cmp[1].datab[1]
datab[4] => cmpchain:cmp[2].datab[0]
datab[5] => cmpchain:cmp[2].datab[1]
datab[6] => cmpchain:cmp[3].datab[0]
datab[7] => cmpchain:cmp[3].datab[1]
datab[8] => cmpchain:cmp[4].datab[0]
datab[9] => cmpchain:cmp[4].datab[1]
datab[10] => cmpchain:cmp[5].datab[0]
datab[11] => cmpchain:cmp[5].datab[1]
datab[12] => cmpchain:cmp[6].datab[0]
datab[13] => cmpchain:cmp[6].datab[1]
datab[14] => cmpchain:cmp[7].datab[0]
datab[15] => cmpchain:cmp[7].datab[1]
aeb <= aeb_node.DB_MAX_OUTPUT_PORT_TYPE
agb <= <UNC>


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[7]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[6]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[5]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[4]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[3]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[2]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[1]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[0]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree
dataa[0] => cmpchain:cmp[0].dataa[0]
dataa[1] => cmpchain:cmp[0].dataa[1]
dataa[2] => cmpchain:cmp[0].dataa[2]
dataa[3] => cmpchain:cmp[0].dataa[3]
dataa[4] => cmpchain:cmp[1].dataa[0]
dataa[5] => cmpchain:cmp[1].dataa[1]
dataa[6] => cmpchain:cmp[1].dataa[2]
dataa[7] => cmpchain:cmp[1].dataa[3]
datab[0] => cmpchain:cmp[0].datab[0]
datab[1] => cmpchain:cmp[0].datab[1]
datab[2] => cmpchain:cmp[0].datab[2]
datab[3] => cmpchain:cmp[0].datab[3]
datab[4] => cmpchain:cmp[1].datab[0]
datab[5] => cmpchain:cmp[1].datab[1]
datab[6] => cmpchain:cmp[1].datab[2]
datab[7] => cmpchain:cmp[1].datab[3]
aeb <= aeb_node.DB_MAX_OUTPUT_PORT_TYPE
agb <= <UNC>


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree|cmpchain:cmp[1]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree|cmpchain:cmp[0]
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree|comptree:sub_comptree
dataa[0] => cmpchain:cmp_end.dataa[0]
dataa[1] => cmpchain:cmp_end.dataa[1]
datab[0] => cmpchain:cmp_end.datab[0]
datab[1] => cmpchain:cmp_end.datab[1]
aeb <= cmpchain:cmp_end.aeb
agb <= <UNC>


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp_end
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|comptree:sub_comptree
dataa[0] => cmpchain:cmp_end.dataa[0]
dataa[1] => cmpchain:cmp_end.dataa[1]
datab[0] => cmpchain:cmp_end.datab[0]
datab[1] => cmpchain:cmp_end.datab[1]
aeb <= cmpchain:cmp_end.aeb
agb <= <UNC>


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|comptree:sub_comptree|cmpchain:cmp_end
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|altshift:aeb_ext_lat_ffs
data[0] => result[0].DATAIN
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|altshift:agb_ext_lat_ffs
data[0] => result[0].DATAIN
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|LPM_COUNTER:$00002
clock => alt_counter_stratix:wysi_counter.clock
clk_en => alt_counter_stratix:wysi_counter.clk_en
aclr => alt_counter_stratix:wysi_counter.aclr
sclr => alt_counter_stratix:wysi_counter.sclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
q[2] <= alt_counter_stratix:wysi_counter.q[2]
q[3] <= alt_counter_stratix:wysi_counter.q[3]
q[4] <= alt_counter_stratix:wysi_counter.q[4]
q[5] <= alt_counter_stratix:wysi_counter.q[5]
q[6] <= alt_counter_stratix:wysi_counter.q[6]
q[7] <= alt_counter_stratix:wysi_counter.q[7]
q[8] <= alt_counter_stratix:wysi_counter.q[8]
q[9] <= alt_counter_stratix:wysi_counter.q[9]
q[10] <= alt_counter_stratix:wysi_counter.q[10]
q[11] <= alt_counter_stratix:wysi_counter.q[11]
q[12] <= alt_counter_stratix:wysi_counter.q[12]
q[13] <= alt_counter_stratix:wysi_counter.q[13]
q[14] <= alt_counter_stratix:wysi_counter.q[14]
q[15] <= alt_counter_stratix:wysi_counter.q[15]
q[16] <= alt_counter_stratix:wysi_counter.q[16]
cout <= alt_counter_stratix:wysi_counter.cout


|uart|Rx:4|clk_pdiv:$00007|LPM_COUNTER:$00002|alt_counter_stratix:wysi_counter
data[0] => counter_cell[0].DATAC
data[1] => counter_cell[1].DATAC
data[2] => counter_cell[2].DATAC
data[3] => counter_cell[3].DATAC
data[4] => counter_cell[4].DATAC
data[5] => counter_cell[5].DATAC
data[6] => counter_cell[6].DATAC
data[7] => counter_cell[7].DATAC
data[8] => counter_cell[8].DATAC
data[9] => counter_cell[9].DATAC
data[10] => counter_cell[10].DATAC
data[11] => counter_cell[11].DATAC
data[12] => counter_cell[12].DATAC
data[13] => counter_cell[13].DATAC
data[14] => counter_cell[14].DATAC
data[15] => counter_cell[15].DATAC
data[16] => counter_cell[16].DATAC
clock => counter_cell[16].CLK
clock => counter_cell[15].CLK
clock => counter_cell[14].CLK
clock => counter_cell[13].CLK
clock => counter_cell[12].CLK
clock => counter_cell[11].CLK
clock => counter_cell[10].CLK
clock => counter_cell[9].CLK
clock => counter_cell[8].CLK
clock => counter_cell[7].CLK
clock => counter_cell[6].CLK
clock => counter_cell[5].CLK
clock => counter_cell[4].CLK
clock => counter_cell[3].CLK
clock => counter_cell[2].CLK
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => counter_cell[16].ENA
clk_en => counter_cell[15].ENA
clk_en => counter_cell[14].ENA
clk_en => counter_cell[13].ENA
clk_en => counter_cell[12].ENA
clk_en => counter_cell[11].ENA
clk_en => counter_cell[10].ENA
clk_en => counter_cell[9].ENA
clk_en => counter_cell[8].ENA
clk_en => counter_cell[7].ENA
clk_en => counter_cell[6].ENA
clk_en => counter_cell[5].ENA
clk_en => counter_cell[4].ENA
clk_en => counter_cell[3].ENA
clk_en => counter_cell[2].ENA
clk_en => counter_cell[1].ENA
clk_en => counter_cell[0].ENA
sload => counter_cell[16].SLOAD
sload => counter_cell[15].SLOAD
sload => counter_cell[14].SLOAD
sload => counter_cell[13].SLOAD
sload => counter_cell[12].SLOAD
sload => counter_cell[11].SLOAD
sload => counter_cell[10].SLOAD
sload => counter_cell[9].SLOAD
sload => counter_cell[8].SLOAD
sload => counter_cell[7].SLOAD
sload => counter_cell[6].SLOAD
sload => counter_cell[5].SLOAD
sload => counter_cell[4].SLOAD
sload => counter_cell[3].SLOAD
sload => counter_cell[2].SLOAD
sload => counter_cell[1].SLOAD
sload => counter_cell[0].SLOAD
sclr => counter_cell[16].SCLR
sclr => counter_cell[15].SCLR
sclr => counter_cell[14].SCLR
sclr => counter_cell[13].SCLR
sclr => counter_cell[12].SCLR
sclr => counter_cell[11].SCLR
sclr => counter_cell[10].SCLR
sclr => counter_cell[9].SCLR
sclr => counter_cell[8].SCLR
sclr => counter_cell[7].SCLR
sclr => counter_cell[6].SCLR
sclr => counter_cell[5].SCLR
sclr => counter_cell[4].SCLR
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[16].ACLR
aclr => counter_cell[15].ACLR
aclr => counter_cell[14].ACLR
aclr => counter_cell[13].ACLR
aclr => counter_cell[12].ACLR
aclr => counter_cell[11].ACLR
aclr => counter_cell[10].ACLR
aclr => counter_cell[9].ACLR
aclr => counter_cell[8].ACLR
aclr => counter_cell[7].ACLR
aclr => counter_cell[6].ACLR
aclr => counter_cell[5].ACLR
aclr => counter_cell[4].ACLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
q[4] <= counter_cell[4].REGOUT
q[5] <= counter_cell[5].REGOUT
q[6] <= counter_cell[6].REGOUT
q[7] <= counter_cell[7].REGOUT
q[8] <= counter_cell[8].REGOUT
q[9] <= counter_cell[9].REGOUT
q[10] <= counter_cell[10].REGOUT
q[11] <= counter_cell[11].REGOUT
q[12] <= counter_cell[12].REGOUT
q[13] <= counter_cell[13].REGOUT
q[14] <= counter_cell[14].REGOUT
q[15] <= counter_cell[15].REGOUT
q[16] <= counter_cell[16].REGOUT
cout <= cout_bit.COMBOUT


|uart|Rx:4|clk_pdiv:$00007|lpm_dff:$00004
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|lpm_dff:$00009
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|Filterx:$00011
clk => filt_tpl:$00000.clk
S_IN[0] => filt_tpl:$00000.f_in
reset => filt_tpl:$00000.reset
preset => filt_tpl:$00000.preset
S_OUT[0] <= F_ARRAY[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|Filterx:$00011|filt_tpl:$00000
CLK => FF[2].CLK
CLK => FF[1].CLK
CLK => FF[0].CLK
CLK => SYNC.CLK
F_IN => FF[0].DATAIN
F_OUT <= SYNC.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|LPM_COUNTER:$00013
clock => alt_counter_stratix:wysi_counter.clock
clk_en => alt_counter_stratix:wysi_counter.clk_en
aclr => alt_counter_stratix:wysi_counter.aclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
q[2] <= alt_counter_stratix:wysi_counter.q[2]
q[3] <= alt_counter_stratix:wysi_counter.q[3]
cout <= alt_counter_stratix:wysi_counter.cout


|uart|Rx:4|LPM_COUNTER:$00013|alt_counter_stratix:wysi_counter
data[0] => counter_cell[0].DATAC
data[1] => counter_cell[1].DATAC
data[2] => counter_cell[2].DATAC
data[3] => counter_cell[3].DATAC
clock => counter_cell[3].CLK
clock => counter_cell[2].CLK
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => counter_cell[3].ENA
clk_en => counter_cell[2].ENA
clk_en => counter_cell[1].ENA
clk_en => counter_cell[0].ENA
sload => counter_cell[3].SLOAD
sload => counter_cell[2].SLOAD
sload => counter_cell[1].SLOAD
sload => counter_cell[0].SLOAD
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
cout <= cout_bit.COMBOUT


|uart|Rx:4|Par_Gen:$00015
D[0] => OUT[1].IN0
D[1] => OUT[1].IN1
D[2] => OUT[2].IN1
D[3] => OUT[3].IN1
D[4] => OUT[4].IN1
D[5] => OUT[5].IN1
D[6] => OUT[6].IN1
D[7] => OUT[7].IN1
ODD/EVEN <= OUT[7].DB_MAX_OUTPUT_PORT_TYPE