uart_hier_info

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

sclr => counter_cell[9].SCLR
sclr => counter_cell[8].SCLR
sclr => counter_cell[7].SCLR
sclr => counter_cell[6].SCLR
sclr => counter_cell[5].SCLR
sclr => counter_cell[4].SCLR
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[16].ACLR
aclr => counter_cell[15].ACLR
aclr => counter_cell[14].ACLR
aclr => counter_cell[13].ACLR
aclr => counter_cell[12].ACLR
aclr => counter_cell[11].ACLR
aclr => counter_cell[10].ACLR
aclr => counter_cell[9].ACLR
aclr => counter_cell[8].ACLR
aclr => counter_cell[7].ACLR
aclr => counter_cell[6].ACLR
aclr => counter_cell[5].ACLR
aclr => counter_cell[4].ACLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
q[4] <= counter_cell[4].REGOUT
q[5] <= counter_cell[5].REGOUT
q[6] <= counter_cell[6].REGOUT
q[7] <= counter_cell[7].REGOUT
q[8] <= counter_cell[8].REGOUT
q[9] <= counter_cell[9].REGOUT
q[10] <= counter_cell[10].REGOUT
q[11] <= counter_cell[11].REGOUT
q[12] <= counter_cell[12].REGOUT
q[13] <= counter_cell[13].REGOUT
q[14] <= counter_cell[14].REGOUT
q[15] <= counter_cell[15].REGOUT
q[16] <= counter_cell[16].REGOUT
cout <= cout_bit.COMBOUT


|uart|TX:5|clk_pdiv:$00001|lpm_dff:$00004
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00003
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00005
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|ShiftReg:$00007
CLK => FF[7].CLK
CLK => FF[6].CLK
CLK => FF[5].CLK
CLK => FF[4].CLK
CLK => FF[3].CLK
CLK => FF[2].CLK
CLK => FF[1].CLK
CLK => FF[0].CLK
ENABLE => FF[7].ENA
ENABLE => FF[6].ENA
ENABLE => FF[5].ENA
ENABLE => FF[4].ENA
ENABLE => FF[3].ENA
ENABLE => FF[2].ENA
ENABLE => FF[1].ENA
ENABLE => FF[0].ENA
DIN => FF[7].DATAIN
Q[0] <= FF[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= FF[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= FF[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= FF[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= FF[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= FF[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= FF[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= FF[7].DB_MAX_OUTPUT_PORT_TYPE
DOUT <= FF[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_mux:$00009
data[0][0] => mux_q8c:auto_generated.data[0]
data[1][0] => mux_q8c:auto_generated.data[1]
data[2][0] => mux_q8c:auto_generated.data[2]
data[3][0] => mux_q8c:auto_generated.data[3]
sel[0] => mux_q8c:auto_generated.sel[0]
sel[1] => mux_q8c:auto_generated.sel[1]
result[0] <= mux_q8c:auto_generated.result[0]


|uart|TX:5|lpm_mux:$00009|mux_q8c:auto_generated
result[0] <= w_result18w.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|LPM_COUNTER:$00011
clock => alt_counter_stratix:wysi_counter.clock
cnt_en => alt_counter_stratix:wysi_counter.cnt_en
aclr => alt_counter_stratix:wysi_counter.aclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
q[2] <= alt_counter_stratix:wysi_counter.q[2]
q[3] <= alt_counter_stratix:wysi_counter.q[3]
q[4] <= alt_counter_stratix:wysi_counter.q[4]
cout <= alt_counter_stratix:wysi_counter.cout


|uart|TX:5|LPM_COUNTER:$00011|alt_counter_stratix:wysi_counter
clock => counter_cell[4].CLK
clock => counter_cell[3].CLK
clock => counter_cell[2].CLK
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => counter_cell[4].ENA
clk_en => counter_cell[3].ENA
clk_en => counter_cell[2].ENA
clk_en => counter_cell[1].ENA
clk_en => counter_cell[0].ENA
cnt_en => counter_cell[4].DATAB
cnt_en => counter_cell[3].DATAB
cnt_en => counter_cell[2].DATAB
cnt_en => counter_cell[1].DATAB
cnt_en => counter_cell[0].DATAB
sclr => counter_cell[4].SCLR
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[4].ACLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
q[4] <= counter_cell[4].REGOUT
cout <= cout_bit.COMBOUT


|uart|TX:5|Par_Gen:$00013
D[0] => OUT[1].IN0
D[1] => OUT[1].IN1
D[2] => OUT[2].IN1
D[3] => OUT[3].IN1
D[4] => OUT[4].IN1
D[5] => OUT[5].IN1
D[6] => OUT[6].IN1
D[7] => OUT[7].IN1
ODD/EVEN <= OUT[7].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00015
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00017
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4
clk => lpm_counter:$00013.clock
clk => filterx:$00011.clk
clk => clk_pdiv:$00007.clk
clk => lpm_dff:$00005.clock
clk => lpm_dff:$00003.clock
clk => lpm_dff:$00001.clock
clk => Rxss~0.IN1
reset => filterx:$00011.preset
reset => lpm_dff:$00001.aclr
reset => Rxss~2.IN1
DIVISOR[0] => clk_pdiv:$00007.d[0]
DIVISOR[1] => clk_pdiv:$00007.d[1]
DIVISOR[2] => clk_pdiv:$00007.d[2]
DIVISOR[3] => clk_pdiv:$00007.d[3]
DIVISOR[4] => clk_pdiv:$00007.d[4]
DIVISOR[5] => clk_pdiv:$00007.d[5]
DIVISOR[6] => clk_pdiv:$00007.d[6]
DIVISOR[7] => clk_pdiv:$00007.d[7]
DIVISOR[8] => clk_pdiv:$00007.d[8]
DIVISOR[9] => clk_pdiv:$00007.d[9]
DIVISOR[10] => clk_pdiv:$00007.d[10]
DIVISOR[11] => clk_pdiv:$00007.d[11]
DIVISOR[12] => clk_pdiv:$00007.d[12]
DIVISOR[13] => clk_pdiv:$00007.d[13]
DIVISOR[14] => clk_pdiv:$00007.d[14]
DIVISOR[15] => clk_pdiv:$00007.d[15]
DIVISOR[16] => clk_pdiv:$00007.d[16]
RxEND <= RxEND~0.DB_MAX_OUTPUT_PORT_TYPE
RxReg[0] <= lpm_dff:$00001.q[0]
RxReg[1] <= lpm_dff:$00001.q[1]
RxReg[2] <= lpm_dff:$00001.q[2]
RxReg[3] <= lpm_dff:$00001.q[3]
RxReg[4] <= lpm_dff:$00001.q[4]
RxReg[5] <= lpm_dff:$00001.q[5]
RxReg[6] <= lpm_dff:$00001.q[6]
RxReg[7] <= lpm_dff:$00001.q[7]
RxStatus[0] <= RxStatus$wire[0].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[1] <= RxStatus$wire[1].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[2] <= RxStatus$wire[2].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[3] <= RxStatus$wire[3].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[4] <= RxStatus$wire[4].DB_MAX_OUTPUT_PORT_TYPE
Rx => filterx:$00011.s_in[0]


|uart|Rx:4|lpm_dff:$00001
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|lpm_dff:$00003
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|lpm_dff:$00005
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007
CLK => lpm_dff:$00004.clock
CLK => lpm_counter:$00002.clock
D[0] => lpm_compare:$00000.datab[0]
D[1] => lpm_compare:$00000.datab[1]
D[2] => lpm_compare:$00000.datab[2]
D[3] => lpm_compare:$00000.datab[3]
D[4] => lpm_compare:$00000.datab[4]
D[5] => lpm_compare:$00000.datab[5]
D[6] => lpm_compare:$00000.datab[6]
D[7] => lpm_compare:$00000.datab[7]
D[8] => lpm_compare:$00000.datab[8]
D[9] => lpm_compare:$00000.datab[9]
D[10] => lpm_compare:$00000.datab[10]
D[11] => lpm_compare:$00000.datab[11]
D[12] => lpm_compare:$00000.datab[12]
D[13] => lpm_compare:$00000.datab[13]
D[14] => lpm_compare:$00000.datab[14]
D[15] => lpm_compare:$00000.datab[15]
D[16] => lpm_compare:$00000.datab[16]
enable => lpm_dff:$00004.enable
enable => lpm_counter:$00002.clk_en
RESET => lpm_counter:$00002.aclr
OUT <= lpm_dff:$00004.q[0]
q[0] <= lpm_counter:$00002.q[0]
q[1] <= lpm_counter:$00002.q[1]
q[2] <= lpm_counter:$00002.q[2]
q[3] <= lpm_counter:$00002.q[3]
q[4] <= lpm_counter:$00002.q[4]
q[5] <= lpm_counter:$00002.q[5]
q[6] <= lpm_counter:$00002.q[6]
q[7] <= lpm_counter:$00002.q[7]
q[8] <= lpm_counter:$00002.q[8]
q[9] <= lpm_counter:$00002.q[9]
q[10] <= lpm_counter:$00002.q[10]
q[11] <= lpm_counter:$00002.q[11]
q[12] <= lpm_counter:$00002.q[12]
q[13] <= lpm_counter:$00002.q[13]
q[14] <= lpm_counter:$00002.q[14]
q[15] <= lpm_counter:$00002.q[15]
q[16] <= lpm_counter:$00002.q[16]


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000
dataa[0] => comptree:comparator.dataa[0]
dataa[1] => comptree:comparator.dataa[1]
dataa[2] => comptree:comparator.dataa[2]
dataa[3] => comptree:comparator.dataa[3]
dataa[4] => comptree:comparator.dataa[4]
dataa[5] => comptree:comparator.dataa[5]
dataa[6] => comptree:comparator.dataa[6]
dataa[7] => comptree:comparator.dataa[7]
dataa[8] => comptree:comparator.dataa[8]
dataa[9] => comptree:comparator.dataa[9]
dataa[10] => comptree:comparator.dataa[10]
dataa[11] => comptree:comparator.dataa[11]
dataa[12] => comptree:comparator.dataa[12]
dataa[13] => comptree:comparator.dataa[13]
dataa[14] => comptree:comparator.dataa[14]
dataa[15] => comptree:comparator.dataa[15]
dataa[16] => comptree:comparator.dataa[16]
datab[0] => comptree:comparator.datab[0]
datab[1] => comptree:comparator.datab[1]
datab[2] => comptree:comparator.datab[2]
datab[3] => comptree:comparator.datab[3]
datab[4] => comptree:comparator.datab[4]
datab[5] => comptree:comparator.datab[5]
datab[6] => comptree:comparator.datab[6]
datab[7] => comptree:comparator.datab[7]
datab[8] => comptree:comparator.datab[8]
datab[9] => comptree:comparator.datab[9]
datab[10] => comptree:comparator.datab[10]
datab[11] => comptree:comparator.datab[11]
datab[12] => comptree:comparator.datab[12]
datab[13] => comptree:comparator.datab[13]
datab[14] => comptree:comparator.datab[14]
datab[15] => comptree:comparator.datab[15]
datab[16] => comptree:comparator.datab[16]
aeb <= aeb_xnode.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_xnode.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator
dataa[0] => cmpchain:cmp[0].dataa[0]
dataa[1] => cmpchain:cmp[0].dataa[1]
dataa[2] => cmpchain:cmp[0].dataa[2]
dataa[3] => cmpchain:cmp[0].dataa[3]
dataa[4] => cmpchain:cmp[0].dataa[4]
dataa[5] => cmpchain:cmp[0].dataa[5]
dataa[6] => cmpchain:cmp[0].dataa[6]
dataa[7] => cmpchain:cmp[0].dataa[7]
dataa[8] => cmpchain:cmp[0].dataa[8]
dataa[9] => cmpchain:cmp[0].dataa[9]
dataa[10] => cmpchain:cmp[0].dataa[10]
dataa[11] => cmpchain:cmp[0].dataa[11]
dataa[12] => cmpchain:cmp[0].dataa[12]
dataa[13] => cmpchain:cmp[0].dataa[13]
dataa[14] => cmpchain:cmp[0].dataa[14]
dataa[15] => cmpchain:cmp[0].dataa[15]
dataa[16] => cmpchain:cmp_end.dataa[0]
datab[0] => cmpchain:cmp[0].datab[0]
datab[1] => cmpchain:cmp[0].datab[1]
datab[2] => cmpchain:cmp[0].datab[2]
datab[3] => cmpchain:cmp[0].datab[3]
datab[4] => cmpchain:cmp[0].datab[4]
datab[5] => cmpchain:cmp[0].datab[5]
datab[6] => cmpchain:cmp[0].datab[6]
datab[7] => cmpchain:cmp[0].datab[7]
datab[8] => cmpchain:cmp[0].datab[8]
datab[9] => cmpchain:cmp[0].datab[9]
datab[10] => cmpchain:cmp[0].datab[10]
datab[11] => cmpchain:cmp[0].datab[11]
datab[12] => cmpchain:cmp[0].datab[12]
datab[13] => cmpchain:cmp[0].datab[13]
datab[14] => cmpchain:cmp[0].datab[14]
datab[15] => cmpchain:cmp[0].datab[15]
datab[16] => cmpchain:cmp_end.datab[0]
aeb <= aeb_node.DB_MAX_OUTPUT_PORT_TYPE
agb <= <UNC>


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|comptree:comparator|cmpchain:cmp[0]