uart_hier_info

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

|uart
RCVD <= UARTCTRL:inst3.RCVD
CLK => UARTCTRL:inst3.CLK
CLK => LPM_COUNTER:inst2.clock
RESET => UARTCTRL:inst3.RESET
RESET => LPM_COUNTER:inst2.aclr
WR <= LPM_COUNTER:inst2.cout
Rx => Rx:4.Rx
Di[0] => UARTCTRL:inst3.Di[0]
Di[1] => UARTCTRL:inst3.Di[1]
Di[2] => UARTCTRL:inst3.Di[2]
Di[3] => UARTCTRL:inst3.Di[3]
Di[4] => UARTCTRL:inst3.Di[4]
Di[5] => UARTCTRL:inst3.Di[5]
Di[6] => UARTCTRL:inst3.Di[6]
Di[7] => UARTCTRL:inst3.Di[7]
SENT <= UARTCTRL:inst3.SENT
INT <= UARTCTRL:inst3.INT
Tx <= TX:5.TX
TXSTATUS <= TX:5.TxSTATUS
TXSTART <= UARTCTRL:inst3.TxStart
TXEND <= TX:5.TxEND
TXRESET <= UARTCTRL:inst3.TxReset
TXCLK <= UARTCTRL:inst3.TxCLK
Do[0] <= UARTCTRL:inst3.Do[0]
Do[1] <= UARTCTRL:inst3.Do[1]
Do[2] <= UARTCTRL:inst3.Do[2]
Do[3] <= UARTCTRL:inst3.Do[3]
Do[4] <= UARTCTRL:inst3.Do[4]
Do[5] <= UARTCTRL:inst3.Do[5]
Do[6] <= UARTCTRL:inst3.Do[6]
Do[7] <= UARTCTRL:inst3.Do[7]
TXCFGREG[0] <= UARTCTRL:inst3.TxCfgReg[0]
TXCFGREG[1] <= UARTCTRL:inst3.TxCfgReg[1]
TXCFGREG[2] <= UARTCTRL:inst3.TxCfgReg[2]
TXCFGREG[3] <= UARTCTRL:inst3.TxCfgReg[3]
TXCFGREG[4] <= UARTCTRL:inst3.TxCfgReg[4]
TXCFGREG[5] <= UARTCTRL:inst3.TxCfgReg[5]
TXCFGREG[6] <= UARTCTRL:inst3.TxCfgReg[6]
TXDIVISOR[0] <= UARTCTRL:inst3.TxDIVISOR[0]
TXDIVISOR[1] <= UARTCTRL:inst3.TxDIVISOR[1]
TXDIVISOR[2] <= UARTCTRL:inst3.TxDIVISOR[2]
TXDIVISOR[3] <= UARTCTRL:inst3.TxDIVISOR[3]
TXDIVISOR[4] <= UARTCTRL:inst3.TxDIVISOR[4]
TXDIVISOR[5] <= UARTCTRL:inst3.TxDIVISOR[5]
TXDIVISOR[6] <= UARTCTRL:inst3.TxDIVISOR[6]
TXDIVISOR[7] <= UARTCTRL:inst3.TxDIVISOR[7]
TXDIVISOR[8] <= UARTCTRL:inst3.TxDIVISOR[8]
TXDIVISOR[9] <= UARTCTRL:inst3.TxDIVISOR[9]
TXDIVISOR[10] <= UARTCTRL:inst3.TxDIVISOR[10]
TXDIVISOR[11] <= UARTCTRL:inst3.TxDIVISOR[11]
TXDIVISOR[12] <= UARTCTRL:inst3.TxDIVISOR[12]
TXDIVISOR[13] <= UARTCTRL:inst3.TxDIVISOR[13]
TXDIVISOR[14] <= UARTCTRL:inst3.TxDIVISOR[14]
TXDIVISOR[15] <= UARTCTRL:inst3.TxDIVISOR[15]
TXDIVISOR[16] <= UARTCTRL:inst3.TxDIVISOR[16]
TXREG[0] <= UARTCTRL:inst3.TxReg[0]
TXREG[1] <= UARTCTRL:inst3.TxReg[1]
TXREG[2] <= UARTCTRL:inst3.TxReg[2]
TXREG[3] <= UARTCTRL:inst3.TxReg[3]
TXREG[4] <= UARTCTRL:inst3.TxReg[4]
TXREG[5] <= UARTCTRL:inst3.TxReg[5]
TXREG[6] <= UARTCTRL:inst3.TxReg[6]
TXREG[7] <= UARTCTRL:inst3.TxReg[7]
XOUT[0] <= TX:5.XOUT[0]
XOUT[1] <= TX:5.XOUT[1]
XOUT[2] <= TX:5.XOUT[2]
XOUT[3] <= TX:5.XOUT[3]


|uart|UARTCTRL:inst3
Di[0] => lpm_dff:$00012.data[0]
Di[1] => lpm_dff:$00012.data[1]
Di[2] => lpm_dff:$00012.data[2]
Di[3] => lpm_dff:$00012.data[3]
Di[4] => lpm_dff:$00012.data[4]
Di[5] => lpm_dff:$00012.data[5]
Di[6] => lpm_dff:$00012.data[6]
Di[7] => lpm_dff:$00012.data[7]
Do[0] <= DOMUX[0].DB_MAX_OUTPUT_PORT_TYPE
Do[1] <= DOMUX[1].DB_MAX_OUTPUT_PORT_TYPE
Do[2] <= DOMUX[2].DB_MAX_OUTPUT_PORT_TYPE
Do[3] <= DOMUX[3].DB_MAX_OUTPUT_PORT_TYPE
Do[4] <= DOMUX[4].DB_MAX_OUTPUT_PORT_TYPE
Do[5] <= DOMUX[5].DB_MAX_OUTPUT_PORT_TYPE
Do[6] <= DOMUX[6].DB_MAX_OUTPUT_PORT_TYPE
Do[7] <= DOMUX[7].DB_MAX_OUTPUT_PORT_TYPE
CLK => RxCLK.DATAIN
CLK => TxCLK.DATAIN
CLK => lpm_dff:$00020.clock
CLK => lpm_dff:$00018.clock
CLK => lpm_dff:$00016.clock
CLK => RxRdss~0.IN1
CLK => TxWrss~0.IN1
RESET => RxReset.DATAIN
RESET => TxReset.DATAIN
RESET => lpm_dff:$00020.aclr
RESET => lpm_dff:$00018.aclr
RESET => lpm_dff:$00016.aclr
RESET => lpm_dff:$00012.aclr
RESET => RxRdss~2.IN1
RESET => TxWrss~2.IN1
A[0] => lpm_mux:$00014.sel[0]
A[1] => lpm_mux:$00014.sel[1]
INT <= lpm_dff:$00020.q[0]
RCVD <= lpm_dff:$00016.q[0]
SENT <= lpm_dff:$00018.q[0]
TxDIVISOR[0] <= DIVd[0].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[1] <= DIVd[1].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[2] <= DIVd[2].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[3] <= DIVd[3].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[4] <= DIVd[4].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[5] <= DIVd[5].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[6] <= DIVd[6].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[7] <= DIVd[7].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[8] <= DIVd[8].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[9] <= DIVd[9].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[10] <= DIVd[10].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[11] <= DIVd[11].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[12] <= DIVd[12].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[13] <= DIVd[13].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[14] <= DIVd[14].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[15] <= DIVd[15].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[16] <= DIVd[16].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[0] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[1] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[2] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[3] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[4] <= <VCC>
TxCfgReg[5] <= <VCC>
TxCfgReg[6] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
TxReg[0] <= lpm_dff:$00012.q[0]
TxReg[1] <= lpm_dff:$00012.q[1]
TxReg[2] <= lpm_dff:$00012.q[2]
TxReg[3] <= lpm_dff:$00012.q[3]
TxReg[4] <= lpm_dff:$00012.q[4]
TxReg[5] <= lpm_dff:$00012.q[5]
TxReg[6] <= lpm_dff:$00012.q[6]
TxReg[7] <= lpm_dff:$00012.q[7]
TxSTATUS => lpm_mux:$00014.data[1][0]
TxEnd => lpm_dff:$00018.data[0]
TxStart <= TxWr2.DB_MAX_OUTPUT_PORT_TYPE
TxReset <= RESET.DB_MAX_OUTPUT_PORT_TYPE
TxCLK <= CLK.DB_MAX_OUTPUT_PORT_TYPE
RxSTATUS[0] => lpm_mux:$00014.data[1][1]
RxSTATUS[1] => lpm_mux:$00014.data[1][2]
RxSTATUS[2] => lpm_mux:$00014.data[1][3]
RxSTATUS[3] => lpm_mux:$00014.data[1][4]
RxSTATUS[4] => lpm_mux:$00014.data[1][5]
RxReg[0] => lpm_mux:$00014.data[0][0]
RxReg[1] => lpm_mux:$00014.data[0][1]
RxReg[2] => lpm_mux:$00014.data[0][2]
RxReg[3] => lpm_mux:$00014.data[0][3]
RxReg[4] => lpm_mux:$00014.data[0][4]
RxReg[5] => lpm_mux:$00014.data[0][5]
RxReg[6] => lpm_mux:$00014.data[0][6]
RxReg[7] => lpm_mux:$00014.data[0][7]
RxDIVISOR[0] <= DIVd[0].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[1] <= DIVd[1].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[2] <= DIVd[2].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[3] <= DIVd[3].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[4] <= DIVd[4].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[5] <= DIVd[5].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[6] <= DIVd[6].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[7] <= DIVd[7].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[8] <= DIVd[8].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[9] <= DIVd[9].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[10] <= DIVd[10].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[11] <= DIVd[11].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[12] <= DIVd[12].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[13] <= DIVd[13].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[14] <= DIVd[14].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[15] <= DIVd[15].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[16] <= DIVd[16].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[0] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[1] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[2] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[3] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[4] <= <VCC>
RxCfgReg[5] <= <VCC>
RxCfgReg[6] <= DMXDo[1][6].DB_MAX_OUTPUT_PORT_TYPE
RxEnd => lpm_dff:$00016.data[0]
RxStart <= RxRd2.DB_MAX_OUTPUT_PORT_TYPE
RxReset <= RESET.DB_MAX_OUTPUT_PORT_TYPE
RxCLK <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00012
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_mux:$00014
data[0][0] => mux_19c:auto_generated.data[0]
data[0][1] => mux_19c:auto_generated.data[1]
data[0][2] => mux_19c:auto_generated.data[2]
data[0][3] => mux_19c:auto_generated.data[3]
data[0][4] => mux_19c:auto_generated.data[4]
data[0][5] => mux_19c:auto_generated.data[5]
data[0][6] => mux_19c:auto_generated.data[6]
data[0][7] => mux_19c:auto_generated.data[7]
data[1][0] => mux_19c:auto_generated.data[8]
data[1][1] => mux_19c:auto_generated.data[9]
data[1][2] => mux_19c:auto_generated.data[10]
data[1][3] => mux_19c:auto_generated.data[11]
data[1][4] => mux_19c:auto_generated.data[12]
data[1][5] => mux_19c:auto_generated.data[13]
data[1][6] => mux_19c:auto_generated.data[14]
data[1][7] => mux_19c:auto_generated.data[15]
data[2][0] => mux_19c:auto_generated.data[16]
data[2][1] => mux_19c:auto_generated.data[17]
data[2][2] => mux_19c:auto_generated.data[18]
data[2][3] => mux_19c:auto_generated.data[19]
data[2][4] => mux_19c:auto_generated.data[20]
data[2][5] => mux_19c:auto_generated.data[21]
data[2][6] => mux_19c:auto_generated.data[22]
data[2][7] => mux_19c:auto_generated.data[23]
data[3][0] => mux_19c:auto_generated.data[24]
data[3][1] => mux_19c:auto_generated.data[25]
data[3][2] => mux_19c:auto_generated.data[26]
data[3][3] => mux_19c:auto_generated.data[27]
data[3][4] => mux_19c:auto_generated.data[28]
data[3][5] => mux_19c:auto_generated.data[29]
data[3][6] => mux_19c:auto_generated.data[30]
data[3][7] => mux_19c:auto_generated.data[31]
sel[0] => mux_19c:auto_generated.sel[0]
sel[1] => mux_19c:auto_generated.sel[1]
result[0] <= mux_19c:auto_generated.result[0]
result[1] <= mux_19c:auto_generated.result[1]
result[2] <= mux_19c:auto_generated.result[2]
result[3] <= mux_19c:auto_generated.result[3]
result[4] <= mux_19c:auto_generated.result[4]
result[5] <= mux_19c:auto_generated.result[5]
result[6] <= mux_19c:auto_generated.result[6]
result[7] <= mux_19c:auto_generated.result[7]


|uart|UARTCTRL:inst3|lpm_mux:$00014|mux_19c:auto_generated
result[0] <= w_result15w.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= w_result45w.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= w_result70w.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= w_result95w.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= w_result120w.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= w_result145w.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= w_result170w.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= w_result195w.DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00016
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00018
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00020
clock => dffs[0].CLK
enable => dffs[0].ENA
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|LPM_COUNTER:inst2
clock => alt_counter_stratix:wysi_counter.clock
aclr => alt_counter_stratix:wysi_counter.aclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
q[2] <= alt_counter_stratix:wysi_counter.q[2]
q[3] <= alt_counter_stratix:wysi_counter.q[3]
q[4] <= alt_counter_stratix:wysi_counter.q[4]
q[5] <= alt_counter_stratix:wysi_counter.q[5]
q[6] <= alt_counter_stratix:wysi_counter.q[6]
q[7] <= alt_counter_stratix:wysi_counter.q[7]
q[8] <= alt_counter_stratix:wysi_counter.q[8]
q[9] <= alt_counter_stratix:wysi_counter.q[9]
q[10] <= alt_counter_stratix:wysi_counter.q[10]
q[11] <= alt_counter_stratix:wysi_counter.q[11]
cout <= alt_counter_stratix:wysi_counter.cout


|uart|LPM_COUNTER:inst2|alt_counter_stratix:wysi_counter
data[0] => counter_cell[0].DATAC
data[1] => counter_cell[1].DATAC
data[2] => counter_cell[2].DATAC
data[3] => counter_cell[3].DATAC
data[4] => counter_cell[4].DATAC
data[5] => counter_cell[5].DATAC
data[6] => counter_cell[6].DATAC
data[7] => counter_cell[7].DATAC
data[8] => counter_cell[8].DATAC
data[9] => counter_cell[9].DATAC
data[10] => counter_cell[10].DATAC
data[11] => counter_cell[11].DATAC
clock => counter_cell[11].CLK
clock => counter_cell[10].CLK
clock => counter_cell[9].CLK
clock => counter_cell[8].CLK
clock => counter_cell[7].CLK
clock => counter_cell[6].CLK
clock => counter_cell[5].CLK
clock => counter_cell[4].CLK
clock => counter_cell[3].CLK
clock => counter_cell[2].CLK
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => counter_cell[11].ENA
clk_en => counter_cell[10].ENA
clk_en => counter_cell[9].ENA
clk_en => counter_cell[8].ENA
clk_en => counter_cell[7].ENA
clk_en => counter_cell[6].ENA
clk_en => counter_cell[5].ENA
clk_en => counter_cell[4].ENA
clk_en => counter_cell[3].ENA
clk_en => counter_cell[2].ENA
clk_en => counter_cell[1].ENA
clk_en => counter_cell[0].ENA
sload => counter_cell[11].SLOAD
sload => counter_cell[10].SLOAD
sload => counter_cell[9].SLOAD
sload => counter_cell[8].SLOAD
sload => counter_cell[7].SLOAD
sload => counter_cell[6].SLOAD
sload => counter_cell[5].SLOAD
sload => counter_cell[4].SLOAD
sload => counter_cell[3].SLOAD
sload => counter_cell[2].SLOAD
sload => counter_cell[1].SLOAD
sload => counter_cell[0].SLOAD
sclr => counter_cell[11].SCLR
sclr => counter_cell[10].SCLR
sclr => counter_cell[9].SCLR
sclr => counter_cell[8].SCLR
sclr => counter_cell[7].SCLR
sclr => counter_cell[6].SCLR
sclr => counter_cell[5].SCLR
sclr => counter_cell[4].SCLR
sclr => counter_cell[3].SCLR
sclr => counter_cell[2].SCLR
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[11].ACLR
aclr => counter_cell[10].ACLR
aclr => counter_cell[9].ACLR
aclr => counter_cell[8].ACLR
aclr => counter_cell[7].ACLR
aclr => counter_cell[6].ACLR
aclr => counter_cell[5].ACLR
aclr => counter_cell[4].ACLR
aclr => counter_cell[3].ACLR
aclr => counter_cell[2].ACLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
q[2] <= counter_cell[2].REGOUT
q[3] <= counter_cell[3].REGOUT
q[4] <= counter_cell[4].REGOUT
q[5] <= counter_cell[5].REGOUT
q[6] <= counter_cell[6].REGOUT
q[7] <= counter_cell[7].REGOUT
q[8] <= counter_cell[8].REGOUT
q[9] <= counter_cell[9].REGOUT
q[10] <= counter_cell[10].REGOUT
q[11] <= counter_cell[11].REGOUT
cout <= cout_bit.COMBOUT


|uart|TX:5
clk => lpm_dff:$00017.clock
clk => lpm_dff:$00015.clock
clk => clk_pdiv:$00001.clk
clk => Txss~0.IN1
reset => shiftreg:$00007.clear
reset => Txss~2.IN1
TxReg[0] => TxSRd[0].IN1
TxReg[1] => TxSRd[1].IN1
TxReg[2] => TxSRd[2].IN1
TxReg[3] => TxSRd[3].IN1
TxReg[4] => TxSRd[4].IN1
TxReg[5] => TxSRd[5].IN1
TxReg[6] => TxSRd[6].IN1
TxReg[7] => TxSRd[7].IN1
DIVISOR[0] => clk_pdiv:$00001.d[0]
DIVISOR[1] => clk_pdiv:$00001.d[1]
DIVISOR[2] => clk_pdiv:$00001.d[2]
DIVISOR[3] => clk_pdiv:$00001.d[3]
DIVISOR[4] => clk_pdiv:$00001.d[4]
DIVISOR[5] => clk_pdiv:$00001.d[5]
DIVISOR[6] => clk_pdiv:$00001.d[6]
DIVISOR[7] => clk_pdiv:$00001.d[7]
DIVISOR[8] => clk_pdiv:$00001.d[8]
DIVISOR[9] => clk_pdiv:$00001.d[9]
DIVISOR[10] => clk_pdiv:$00001.d[10]
DIVISOR[11] => clk_pdiv:$00001.d[11]