cpu.map.eqn

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

--M7_data_out[1] is tx8:u_tx8|wri_reg8:u_write_data|data_out[1]
--operation mode is normal

M7_data_out[1]_lut_out = A1L23;
M7_data_out[1] = DFFEA(M7_data_out[1]_lut_out, iow, rst, , K1L8, , );


--K1L4 is tx8:u_tx8|Mux~5
--operation mode is normal

K1L4 = P01_q[0] & K1L3 & M7_data_out[1] # !K1L3 & M7_data_out[7] # !P01_q[0] & K1L3;


--K1L21 is tx8:u_tx8|tx~174
--operation mode is normal

K1L21 = P01_q[3] & P01_q[2] # P01_q[1] # K1L4;


--M7_data_out[4] is tx8:u_tx8|wri_reg8:u_write_data|data_out[4]
--operation mode is normal

M7_data_out[4]_lut_out = A1L201;
M7_data_out[4] = DFFEA(M7_data_out[4]_lut_out, iow, rst, , K1L8, , );


--M7_data_out[3] is tx8:u_tx8|wri_reg8:u_write_data|data_out[3]
--operation mode is normal

M7_data_out[3]_lut_out = A1L97;
M7_data_out[3] = DFFEA(M7_data_out[3]_lut_out, iow, rst, , K1L8, , );


--M7_data_out[2] is tx8:u_tx8|wri_reg8:u_write_data|data_out[2]
--operation mode is normal

M7_data_out[2]_lut_out = A1L65;
M7_data_out[2] = DFFEA(M7_data_out[2]_lut_out, iow, rst, , K1L8, , );


--K1L5 is tx8:u_tx8|Mux~6
--operation mode is normal

K1L5 = P01_q[1] & P01_q[0] # !P01_q[1] & P01_q[0] & M7_data_out[3] # !P01_q[0] & M7_data_out[2];


--M7_data_out[5] is tx8:u_tx8|wri_reg8:u_write_data|data_out[5]
--operation mode is normal

M7_data_out[5]_lut_out = A1L811;
M7_data_out[5] = DFFEA(M7_data_out[5]_lut_out, iow, rst, , K1L8, , );


--K1L6 is tx8:u_tx8|Mux~7
--operation mode is normal

K1L6 = P01_q[1] & K1L5 & M7_data_out[5] # !K1L5 & M7_data_out[4] # !P01_q[1] & K1L5;


--K1_en_tx is tx8:u_tx8|en_tx
--operation mode is normal

K1_en_tx_lut_out = VCC;
K1_en_tx = DFFEA(K1_en_tx_lut_out, iow, !K1L7, , K1L8, , );


--U4L31 is tx8:u_tx8|data_clk:u_data_clk|gen_clk~2
--operation mode is normal

U4L31 = !K1_en_tx # !rst;


--K1L31 is tx8:u_tx8|tx~175
--operation mode is normal

K1L31 = K1L21 # U4L31 # P01_q[2] & K1L6;


--K1L41 is tx8:u_tx8|tx~176
--operation mode is normal

K1L41 = P01_q[1] & K1L4 # !P01_q[1] & !P01_q[3] & !P01_q[0];


--K1L51 is tx8:u_tx8|tx~177
--operation mode is normal

K1L51 = P01_q[4] # K1L31 # K1L41 & !P01_q[2];


--W1L3 is read_return_pre_set:u_rx_tx|tx16:u_tx|LessThan~76
--operation mode is normal

W1L3 = W1L81 & !P6_q[1] # !P6_q[0] # !P6_q[4];


--U3_data_clk is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|data_clk
--operation mode is normal

U3_data_clk_lut_out = !U3_data_clk;
U3_data_clk = DFFEA(U3_data_clk_lut_out, D1_P1MHz, !W1L61, , U3L81, , );


--V1_t_data[10] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[10]
--operation mode is normal

V1_t_data[10]_lut_out = set_rx;
V1_t_data[10] = DFFEA(V1_t_data[10]_lut_out, U2_data_clk, rst, , V1L62, , );


--E1L3 is write_reg:u_read_write|process2~0
--operation mode is normal

E1L3 = V1_t_data[10] # !rst;


--K1L01 is tx8:u_tx8|reduce_nor~23
--operation mode is normal

K1L01 = M4_data_out[3] & A1L442 & !M4_data_out[4] & !M4_data_out[5];


--E1L9 is write_reg:u_read_write|reduce_nor~5
--operation mode is normal

E1L9 = !M4_data_out[1] & !M4_data_out[0] & M4_data_out[2] & K1L01;


--C1L03 is generate_int:u_int|reduce_nor~78
--operation mode is normal

C1L03 = A1L442 & !M4_data_out[4] & !M4_data_out[3] & !M4_data_out[5];


--E1L8 is write_reg:u_read_write|reduce_nor~4
--operation mode is normal

E1L8 = !M4_data_out[2] & M4_data_out[0] & M4_data_out[1] & C1L03;


--U2_data_clk is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|data_clk
--operation mode is normal

U2_data_clk_lut_out = !U2_data_clk;
U2_data_clk = DFFEA(U2_data_clk_lut_out, D1_P1MHz, !U2L31, , U2L91, , );


--P5_q[0] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

P5_q[0]_lut_out = (P5L21 $ P5_q[0]) & VCC;
P5_q[0] = DFFEA(P5_q[0]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L3 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

P5L3 = CARRY(P5_q[0]);


--P5_q[3] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

P5_q[3]_lut_out = (P5_q[3] $ (P5L21 & P5L7)) & VCC;
P5_q[3] = DFFEA(P5_q[3]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L9 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

P5L9 = CARRY(P5_q[3] & P5L7);


--V1_en_rx is read_return_pre_set:u_rx_tx|rx16:u_rx|en_rx
--operation mode is normal

V1_en_rx_lut_out = VCC;
V1_en_rx = DFFEA(V1_en_rx_lut_out, !set_rx, !V1L8, , V1L6, , );


--P5_q[2] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

P5_q[2]_lut_out = (P5_q[2] $ (P5L21 & P5L5)) & VCC;
P5_q[2] = DFFEA(P5_q[2]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L7 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

P5L7 = CARRY(P5_q[2] & P5L5);


--P5_q[4] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

P5_q[4]_lut_out = (P5_q[4] $ (P5L21 & P5L9)) & VCC;
P5_q[4] = DFFEA(P5_q[4]_lut_out, !U2_data_clk, !U2L31, , , , );


--V1L21 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[0]~255
--operation mode is normal

V1L21 = V1_en_rx & !P5_q[2] & !P5_q[4];


--P5_q[1] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

P5_q[1]_lut_out = (P5_q[1] $ (P5L21 & P5L3)) & VCC;
P5_q[1] = DFFEA(P5_q[1]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L5 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

P5L5 = CARRY(P5_q[1] & P5L3);


--V1L42 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[9]~6
--operation mode is normal

V1L42 = P5_q[0] & P5_q[3] & V1L21 & !P5_q[1];


--E1L11 is write_reg:u_read_write|reduce_nor~7
--operation mode is normal

E1L11 = !M4_data_out[0] & K1L01 & M4_data_out[2] & M4_data_out[1];


--E1L7 is write_reg:u_read_write|reduce_nor~3
--operation mode is normal

E1L7 = !M4_data_out[0] & !M4_data_out[2] & C1L03 & M4_data_out[1];


--V1L92 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[13]~256
--operation mode is normal

V1L92 = P5_q[2] & V1_en_rx & !P5_q[4];


--V1L02 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[4]~8
--operation mode is normal

V1L02 = V1L92 & !P5_q[0] & !P5_q[1] & !P5_q[3];


--V1L81 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[3]~9
--operation mode is normal

V1L81 = P5_q[0] & V1L21 & P5_q[1] & !P5_q[3];


--P5L11 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[4]~17
--operation mode is normal

P5L11 = !P5_q[2] & !P5_q[1] & !P5_q[3];


--V1L53 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[16]~1
--operation mode is normal

V1L53 = P5_q[4] & V1_en_rx & P5L11 & !P5_q[0];


--V1L41 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[1]~11
--operation mode is normal

V1L41 = P5_q[0] & V1L21 & !P5_q[1] & !P5_q[3];


--V1L33 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[15]~2
--operation mode is normal

V1L33 = P5_q[0] & P5_q[1] & P5_q[3] & V1L92;


--V1L61 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[2]~10
--operation mode is normal

V1L61 = P5_q[1] & V1L21 & !P5_q[3] & !P5_q[0];


--V1L82 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[13]~4
--operation mode is normal

V1L82 = P5_q[3] & V1L92 & P5_q[0] & !P5_q[1];


--E1L01 is write_reg:u_read_write|reduce_nor~6
--operation mode is normal

E1L01 = !M4_data_out[1] & M4_data_out[2] & M4_data_out[0] & K1L01;


--V1L13 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[14]~3
--operation mode is normal

V1L13 = P5_q[1] & P5_q[3] & V1L92 & !P5_q[0];


--G1_t_start_tx is read_return_pre_set:u_rx_tx|t_start_tx
--operation mode is normal

G1_t_start_tx_lut_out = G1L42 & G1_t_start_tx # !G1L31;
G1_t_start_tx = DFFEA(G1_t_start_tx_lut_out, D1_P1MHz, !G1L4, , G1L52, , );


--W1_end_tx is read_return_pre_set:u_rx_tx|tx16:u_tx|end_tx
--operation mode is normal

W1_end_tx_lut_out = VCC;
W1_end_tx = DFFEA(W1_end_tx_lut_out, !U3_data_clk, !W1L61, , W1L91, , );


--W1L51 is read_return_pre_set:u_rx_tx|tx16:u_tx|process0~0
--operation mode is normal

W1L51 = W1_end_tx # !rst;


--E1L6 is write_reg:u_read_write|reduce_nor~2
--operation mode is normal

E1L6 = !M4_data_out[1] & !M4_data_out[0] & M4_data_out[2] & C1L03;


--M3_data_out[2] is write_reg:u_read_write|wri_reg8:u_a3_reg|data_out[2]
--operation mode is normal

M3_data_out[2]_lut_out = A1L65;
M3_data_out[2] = DFFEA(M3_data_out[2]_lut_out, iow, rst, , E1L6, , );


--M3_data_out[1] is write_reg:u_read_write|wri_reg8:u_a3_reg|data_out[1]
--operation mode is normal

M3_data_out[1]_lut_out = A1L23;
M3_data_out[1] = DFFEA(M3_data_out[1]_lut_out, iow, rst, , E1L6, , );


--B1_st[0] is do_adc:u_ad|st[0]
--operation mode is normal

B1_st[0]_lut_out = B1_st[2] & B1L251 & !N1_adc_state[7] # !B1_st[2] & B1L151;
B1_st[0] = DFFEA(B1_st[0]_lut_out, p12mhz, rst, , , , );


--B1_st[1] is do_adc:u_ad|st[1]
--operation mode is normal

B1_st[1]_lut_out = B1_st[0] & B1L341 & !B1L351 # !B1L341 & !B1_st[1] # !B1_st[0] & B1L341;
B1_st[1] = DFFEA(B1_st[1]_lut_out, p12mhz, rst, , , , );


--B1_st[2] is do_adc:u_ad|st[2]
--operation mode is normal

B1_st[2]_lut_out = B1_st[2] & B1L441 & B1L041 # !B1L441 & !B1L931 # !B1_st[2] & B1L441;
B1_st[2] = DFFEA(B1_st[2]_lut_out, p12mhz, rst, , , , );


--B1_st[3] is do_adc:u_ad|st[3]
--operation mode is normal

B1_st[3]_lut_out = B1_st[3] & B1L541 & B1L651 # !B1L541 & B1L941 # !B1_st[3] & B1L541;
B1_st[3] = DFFEA(B1_st[3]_lut_out, p12mhz, rst, , , , );


--B1L431 is do_adc:u_ad|Mux~715
--operation mode is normal

B1L431 = !B1_st[1] & !B1_st[3] & B1_st[0] $ !B1_st[2];


--B1L841 is do_adc:u_ad|Mux~1961
--operation mode is normal

B1L841 = B1_st[2] & !B1_st[3];


--P1L71 is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[7]~1
--operation mode is normal

P1L71 = B1_st[0] & B1L841 & !B1_st[1] # !B1L431;


--B1L851 is do_adc:u_ad|reduce_nor~0
--operation mode is normal

B1L851 = !M4_data_out[2] & !M4_data_out[1] & !M4_data_out[0] & C1L03;


--B1_t_can_con_adc_end is do_adc:u_ad|t_can_con_adc_end
--operation mode is normal

B1_t_can_con_adc_end_lut_out = B1L731;
B1_t_can_con_adc_end = DFFEA(B1_t_can_con_adc_end_lut_out, p12mhz, rst, , B1L531, , );


--B1L861 is do_adc:u_ad|setup_adc_tag~0
--operation mode is normal

B1L861 = B1_t_can_con_adc_end # !rst;


--B1L071 is do_adc:u_ad|setup_adc_tag~40
--operation mode is normal

B1L071 = A1L151 # M4_data_out[2] # M4_data_out[1] # !M4_data_out[0];


--B1L171 is do_adc:u_ad|setup_adc_tag~41
--operation mode is normal

B1L171 = B1L071 # !A1L5 # !A1L23 # !A1L65;


--H1L3 is time_out:u_time_out|reduce_nor~178
--operation mode is normal

H1L3 = !A1L811 & !A1L201 & !A1L531 & !A1L97;


--B1L961 is do_adc:u_ad|setup_adc_tag~1
--operation mode is normal

B1L961 = !B1L171 & C1L03 & H1L3;


--N1_st[0] is do_adc:u_ad|sig_adc:u_sig_adc|st[0]
--operation mode is normal

N1_st[0]_lut_out = N1_st[3] & N1L221 # N1L521 # !N1_st[3] & N1L59;
N1_st[0] = DFFEA(N1_st[0]_lut_out, p12mhz, rst, , , , );


--N1_st[2] is do_adc:u_ad|sig_adc:u_sig_adc|st[2]
--operation mode is normal

N1_st[2]_lut_out = N1L721 # N1L921 & N1L65 # !N1_st[2];