data_clk.vhd

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity data_clk is port (
		rst				: in std_logic;
		p1mhz			: in std_logic;
		can_data_clk	: in std_logic;
		data_clk		: out std_logic		
);
end entity;

architecture clk of data_clk is

----------------------------------------------
signal clk_cnt : integer range 0 to 512;
--4800hz
constant clk_cnt_limit : integer := 207; 
signal t_clk : std_logic;


begin

data_clk <= t_clk;
		
gen_clk : process(rst,p1mhz,can_data_clk)
begin
	if rst='0' or can_data_clk = '0' then
		clk_cnt <= 0;
		t_clk <= '1';
	else	
		if rising_edge(p1mhz) then	
			if  can_data_clk = '1' then
				if clk_cnt < clk_cnt_limit then
					clk_cnt <= clk_cnt + 1;
				elsif clk_cnt = clk_cnt_limit then
					clk_cnt <= 0;
					t_clk <= not t_clk;
				end if;	
			end if;
		end if;
	end if;			
end process;

end architecture;