generate_int.vhd

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

LIBRARY IEEE;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity generate_int is port(
			rst					: in std_logic;
			p1mhz				: in std_logic;
			urgency_put_opt_in	: in std_logic;
			ready_reset_opt_in	: in std_logic;
			urgency_put_opt_inx	: out std_logic;
			ready_reset_opt_inx	: out std_logic;
			sa					: in std_logic_vector(15 downto 0);
			iow					: in std_logic;
			ad_in				: in std_logic_vector(7 downto 0);
			p1khz 				: in std_logic			
);
end entity;

architecture int of generate_int is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;
		
------------------------------
signal cnt_urgency_put : integer range 0 to 51;
signal urgency_put_tag,urgency_put_tag_end : std_logic;
constant cnt_urgency_put_limit : integer := 50;
-----------------------------
signal cnt_ready_reset : integer range 0 to 51;
signal ready_reset_tag,ready_reset_tag_end : std_logic;
constant cnt_ready_reset_limit : integer := 50;
---------------------------------
signal cs_com : std_logic;
signal com : std_logic_vector(7 downto 0);

begin

cs_com <= '0' when sa=x"c007" else '1';
u_com : wri_reg8 port map(
		iow			=> iow,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> cs_com,--: in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> com--: out std_logic_vector(7 downto 0)
		);

urgency_put_opt_inx <= '0' when urgency_put_tag = '1' and com=x"88" and 
		cnt_urgency_put = cnt_urgency_put_limit-1 and urgency_put_opt_in = '0' else '1';
ready_reset_opt_inx <= '0' when ready_reset_tag = '1' and com=x"88" and
		cnt_ready_reset = cnt_ready_reset_limit-1 and ready_reset_opt_in = '1' else '1';

setup_urgency_put_tag : process(rst,urgency_put_tag_end,urgency_put_opt_in)
begin
	if rst='0' or urgency_put_tag_end = '1' then
		urgency_put_tag <= '0';
	else
		if falling_edge(urgency_put_opt_in) then	
			urgency_put_tag <= '1';
		end if;
	end if;		
end process;

cnt_urgency_put_tag : process(rst,p1khz,urgency_put_tag)
begin
	if rst='0' or urgency_put_tag = '0' then
		cnt_urgency_put <= 0;
		urgency_put_tag_end <= '0';
 	else
		if rising_edge(p1khz) then	
			if urgency_put_tag = '1' then
				if cnt_urgency_put < cnt_urgency_put_limit then
					cnt_urgency_put <= cnt_urgency_put + 1;
				elsif cnt_urgency_put = cnt_urgency_put_limit then	
					cnt_urgency_put <= 0;
					urgency_put_tag_end <= '1';
				end if;
			end if;
		end if;
	end if;				
end process;
-------------------------------------------------------------------

setup_ready_reset_tag : process(rst,ready_reset_tag_end,ready_reset_opt_in)
begin
	if rst='0' or ready_reset_tag_end = '1' then
		ready_reset_tag <= '0';
	else
		if falling_edge(ready_reset_opt_in) then	
			ready_reset_tag <= '1';
		end if;
	end if;		
end process;

cnt_ready_reset_tag : process(rst,p1khz,ready_reset_tag)
begin
	if rst='0' or ready_reset_tag = '0' then
		ready_reset_tag_end <= '0';
		cnt_ready_reset <= 0;
	else
		if falling_edge(p1khz) then	
			if ready_reset_tag = '1' then
				if cnt_ready_reset < cnt_ready_reset_limit then
					cnt_ready_reset<= cnt_ready_reset + 1;
				elsif cnt_ready_reset = cnt_ready_reset_limit then
					ready_reset_tag_end <= '1';	
					cnt_ready_reset <= 0;
				end if;
			end if;
		end if;
	end if;				
end process;

end architecture;