📄 read_return_pre_set.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity read_return_pre_set is port(
rst : in std_logic;
----------来自预置控制器的参数
cm_code : out std_logic_vector(3 downto 0);
mode : out std_logic;--和方式选择
set_key : out std_logic;
sd_code : out std_logic_vector(3 downto 0);--包括sd和设定开关
--------CPU要写的数据------------------------------
cm_err_code : in std_logic_vector(3 downto 0);--cm出错编码
sd_err_code : in std_logic_vector(3 downto 0);--sd出错编码
--------回送方式标志位--------------
--0=正常数据回送,1=错误码回送
TC : in std_logic;
--------状态灯-----
y7b_err_led : in std_logic;
y7b_put_led : in std_logic;
y7b_ready_led : in std_logic;
p1mhz : in std_logic;
set_rx : in std_logic;
set_tx : out std_logic;
-------使预置控制器的mode led闪动------------
flash_mode_led : in std_logic;
rst_flash_mode_led : out std_logic;--来自预置控制器串行16位的第rx(9)位
flash_ready_led : in std_logic;--使准备灯,cm,sd闪烁。
--使CM,SD的回送值从cm_err_code,sd_err_code取出
XT : IN STD_LOGIC;
XT_MODE : IN STD_lOGIC--用于CPU回送
);
end entity;
architecture read_return of read_return_pre_set is
component rx16 is port(
rst : in std_logic;
p1mhz : in std_logic;
rx : in std_logic;
data_out : out std_logic_vector(15 downto 0);
rx_tag : out std_logic;
rst_rx : in std_logic
);
end component;
component tx16 is port(
rst : in std_logic;
p1mhz : in std_logic;
data_in : in std_logic_vector(15 downto 0);
tx : out std_logic;
start_tx : in std_logic;
on_tx : out std_logic
);
end component;
signal t_rx_temp : std_logic_vector(15 downto 0);
signal t_tx_temp : std_logic_vector(15 downto 0);
signal t_sd_code : std_logic_vector(2 downto 0);
signal t_rx_tag : std_logic;
signal t_beg_rst_rx , t_end_rst_rx : std_logic;
signal rx_cnt : integer range 0 to 60;
signal temp_sd : std_logic_vector(2 downto 0);
signal t_rst_rx : std_logic;
signal t_start_tx : std_logic;
signal t_on_tx : std_logic;
signal t_lock_pre_set_key : std_logic;
begin
----------------以下是从串口得到数据,发送到cm_code_out和sd_code_out
--接着发送数据到串口sd_code_in,cm_code_in
u_rx : rx16 port map(
rst => rst,--: in std_logic;
p1mhz => p1mhz,--: in std_logic;
rx => set_rx,--: in std_logic;
data_out => t_rx_temp,--: out std_logic_vector(15 downto 0);
rx_tag => t_rx_tag,--: out std_logic;
rst_rx => t_rst_rx--: in std_logic
);
setup_rst_rx : process(rst,t_end_rst_rx,t_rx_tag)
begin
if rst = '0' or t_end_rst_rx = '1' then
t_beg_rst_rx <= '0' ;
else
if rising_edge (t_rx_tag) then
t_beg_rst_rx <= '1' ;
end if;
end if;
end process;
process(rst,t_rx_tag,p1mhz,t_beg_rst_rx)
begin
if rst='0' or t_beg_rst_rx = '0' then
t_end_rst_rx <= '0';
t_rst_rx <= '1';
rx_cnt <= 0;
t_start_tx <= '0';
else
if rising_edge(p1mhz) then
if t_beg_rst_rx = '1' then
if rx_cnt < 5 then
rx_cnt <= rx_cnt + 1;
t_rst_rx <= '1';
elsif rx_cnt < 7 then
rx_cnt <= rx_cnt + 1;
t_rst_rx <= '0';
elsif rx_cnt < 12 then
t_rst_rx <= '1';
rx_cnt <= rx_cnt + 1;
elsif rx_cnt < 27 then
rx_cnt <= rx_cnt + 1;
elsif rx_cnt < 37 then
t_start_tx <= '1';
rx_cnt <= rx_cnt + 1;
elsif rx_cnt < 43 then
rx_cnt <= rx_cnt + 1;
elsif rx_cnt = 43 then
t_start_tx <= '0';
rx_cnt <= 0;
t_end_rst_rx <= '1';
end if;
end if;
end if;
end if;
end process;
cm_code <= t_rx_temp(15 downto 12);
-----------送到io component 使flash_mode_led复位----------------------
rst_flash_mode_led <= t_rx_temp(9);
mode <= t_rx_temp(8);
set_key <= t_rx_temp(7);
sd_code <= t_rx_temp(3 downto 0) ;
-----------以下是发送数据到串口--2007-11-12,9:02
t_tx_temp(15 downto 12) <= cm_err_code when tc='1' OR XT='1' else t_rx_temp(15 downto 12);
t_tx_temp(11) <= TC;
t_tx_temp(10) <= flash_ready_led;--使准备,cm,sd闪烁
-------使预置控制器的mode led闪动------------
t_tx_temp(9) <= flash_mode_led;
t_tx_temp(8) <= XT_MODE WHEN XT='1' ELSE t_rx_temp(8);--cir_snk 开关值回送
t_tx_temp(7) <= '0';
t_tx_temp(6) <= y7b_err_led;--故障灯
t_tx_temp(5) <= y7b_ready_led;--准备灯
t_tx_temp(4) <= y7b_put_led; --,投放灯
t_tx_temp(3 downto 0) <= sd_err_code when tc='1' OR XT='1' else t_rx_temp(3 downto 0) ;
u_tx : tx16 port map(
rst => rst,--: in std_logic;
p1mhz => p1mhz,--: in std_logic;
data_in => t_tx_temp ,--: in std_logic_vector(15 downto 0);
tx => set_tx,--: out std_logic;
start_tx => t_start_tx,--: in std_logic;
on_tx => t_on_tx--: out std_logic
);
end architecture ;
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