do_adc.vhd

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

sel_ad_channel : process(t_ch,ad_data_lchk,ad_data_sd,ad_data_cm,
		ad_data_P28,ad_data_N28,ad_data_V5)
		
begin
	if t_ch = x"00" then
		x_ad_data <= ad_data_lchk;
	elsif t_ch = x"01" then
		x_ad_data <= ad_data_sd;
	elsif t_ch = x"02" then
		x_ad_data <= ad_data_cm;
	elsif t_ch = x"03" then
		x_ad_data <= ad_data_P28;
	elsif t_ch <= x"04" then
		x_ad_data <= ad_data_N28;
	elsif t_ch = x"05" then
		x_ad_data <= ad_data_V5;
	else
		x_ad_data <= x"000";					
	end if; 
end process;

lchk_level <= t_lchk_level; 
p28v_level <= t_p28v_level;
n28v_level <= t_n28v_level;
ref5v_level <= t_ref5v_level;	
cm_level <= t_cm_level;
sd_level <= t_sd_level;	

sel_cda : process(t_ch,t_can_con_adc,t_cda)
begin
	if t_can_con_adc = '1' then
		cda <= t_cda(2 downto 0);
	else
		cda <= t_ch(2 downto 0);
	end if;	
end process;

generate_lchk_level : process(ad_data_lchk)
begin
	if ad_data_lchk = no_y7b then
		t_lchk_level <= "11";
	elsif ad_data_lchk >= no_lock_l and ad_data_lchk <= no_lock_h then
		t_lchk_level <= "01";	 
	elsif ad_data_lchk >= on_lock_l and ad_data_lchk <= on_lock_h then
		t_lchk_level <= "10";	 	
	else
		t_lchk_level <= "00";	
	end if;	
end process;

gen_sd_level : process(ad_data_sd)
begin
	if ad_data_sd >= sdl1 and ad_data_sd <= sdh1 then
		t_sd_level <= "001";
	elsif ad_data_sd >= sdl2 and ad_data_sd <= sdh2 then
		t_sd_level <= "010";			  
	elsif ad_data_sd >= sdl3 and ad_data_sd <= sdh3 then
		t_sd_level <= "011";			  
	elsif ad_data_sd >= sdl4 and ad_data_sd <= sdh4 then
		t_sd_level <= "100";			  
	elsif ad_data_sd >= sdl5 and ad_data_sd <= sdh5 then
		t_sd_level <= "101";			  
	elsif ad_data_sd >= sdl6 and ad_data_sd <= sdh6 then
		t_sd_level <= "110";			  
	elsif ad_data_sd >= sdl7 and ad_data_sd <= sdh7 then
		t_sd_level <= "111";			  
	else
		t_sd_level <= "000";
	end if;	 		
end process;

gen_cm_level : process(ad_data_cm)
begin
	if ad_data_cm >= cml1 and ad_data_cm <= cmh1 then
		t_cm_level <= x"1";
	elsif ad_data_cm >= cml2 and ad_data_cm <= cmh2 then
		t_cm_level <= x"2";	
	elsif ad_data_cm >= cml3 and ad_data_cm <= cmh3 then
		t_cm_level <= x"3";	
	elsif ad_data_cm >= cml4 and ad_data_cm <= cmh4 then
		t_cm_level <= x"4";	
	elsif ad_data_cm >= cml5 and ad_data_cm <= cmh5 then
		t_cm_level <= x"5";	
	elsif ad_data_cm >= cml6 and ad_data_cm <= cmh6 then
		t_cm_level <= x"6";	
	elsif ad_data_cm >= cml7 and ad_data_cm <= cmh7 then
		t_cm_level <= x"7";	
	elsif ad_data_cm >= cml8 and ad_data_cm <= cmh8 then
		t_cm_level <= x"8";	
	elsif ad_data_cm >= cml9 and ad_data_cm <= cmh9 then
		t_cm_level <= x"9";	
	elsif ad_data_cm >= cml10 and ad_data_cm <= cmh10 then
		t_cm_level <= x"a";	
	elsif ad_data_cm >= cml11 and ad_data_cm <= cmh11 then
		t_cm_level <= x"b";	
	elsif ad_data_cm >= cml12 and ad_data_cm <= cmh12 then
		t_cm_level <= x"c";	
	else
		t_cm_level <= x"0";	
	end if;	
end process;

t_p28v_level <= '0' when  ad_data_P28 >= p28v_l and ad_data_P28 <= p28v_h else '1';
t_n28v_level <= '0' when  ad_data_n28 >= n28v_l and ad_data_n28 <= n28v_h else '1';
t_ref5v_level <= '0' when  ad_data_V5 >= ref5v_l and ad_data_V5 <= ref5v_h else '1';

u_sig_adc: sig_adc port map(
		rst				=> rst,--: in std_logic;
		sa				=> sa,--: in std_logic_vector(15 downto 0);
		ad_in			=> ad_in,--: in std_logic_vector(7 downto 0);
		can_adc			=> t_sig_adc,--: in std_logic;
		iow				=> iow,--: in std_logic;
		p12mhz			=> p12mhz,--: in std_logic;
		eoc_state		=> eoc_state,--: in std_logic;
		sd				=> sd,--: in std_logic_vector(7 downto 0);
		rd_adl			=> rd_adl,--: out std_logic;
		rd_adh			=> rd_adh,-- out std_logic;
		start_ad 		=> start_ad,--: out std_logic;
	--ad 转换状态。00=转换结束；11=转换超时。	
		adc_state		=> t_adc_state,--: out std_logic_vector(7 downto 0);
		ad_data			=> t_ad_data--: out std_logic_vector(11 downto 0);


);

setup_adc_tag : process(rst,sa,iow,ad_in,t_can_con_adc_end)
begin
	if rst='0' or t_can_con_adc_end = '1' then
		t_can_con_adc <= '0';
	else
		if rising_edge(iow) then
			if sa=x"c001" and ad_in = x"07" then
				t_can_con_adc <= '1';
			end if;
		end if;
	end if;			
end process;


process(rst,p12mhz,t_can_con_adc,st)
begin
	if rst='0' then
		st <= st_idle;
		ad_data_lchk <= x"000";
		ad_data_sd <= x"000";
		ad_data_cm <= x"000";
		ad_data_P28 <= x"000";
		ad_data_N28 <= x"000";
		ad_data_V5	<= x"000";
		t_can_con_adc_end <= '0';
		t_cda <= x"00";
		t_sig_adc <= '1';
		adc_state <= x"00";
	else
		if rising_edge(p12mhz) then	
			case st is
				when st_idle =>
					t_cda <= x"00";
					t_sig_adc <= '1';
					t_can_con_adc_end <= '0';
					if t_can_con_adc = '1' then
						st <= st_start_con_adc;
					else
						st <= st_idle;
					end if;
				when st_start_con_adc =>
					t_sig_adc <= '1';
					st <= st_start_con_adc_wait;
				when st_start_con_adc_wait =>
					t_sig_adc <= '0';	
					st <= st_start_con_adc_wait0;
				when st_start_con_adc_wait0 => --等待ad完成
					t_sig_adc <= '1';
					st <= st_start_con_adc_wait1x0;
				when st_start_con_adc_wait1x0 =>
					if t_adc_state = x"00" then
						st <= st_start_con_adc_wait1x;
					else
						st <= st_start_con_adc_wait1x0;
					end if;			
				when st_start_con_adc_wait1x => 
					if t_adc_state = x"00" then
						st <= st_start_con_adc_wait1x;
					else
						st <= st_start_con_adc_wait1;
					end if;		
				when st_start_con_adc_wait1 =>	
					if t_adc_state = x"80" then
						st <= st_read_adc_data;
					elsif t_adc_state = x"03" then
						st <= st_adc_error;
					else	
						st <= st_adc_end;
					end if;
				when st_read_adc_data =>
					case t_cda(2 downto 0) is
						when "000" =>
							ad_data_lchk <= t_ad_data;
						when "001" =>
							ad_data_sd	<= t_ad_data;
						when "010" =>
							ad_data_cm  <= t_ad_data;
						when "011" =>
							ad_data_P28	 <= t_ad_data;
						when "100" =>
							ad_data_N28	 <= t_ad_data;
						when "101" =>
							ad_data_V5 	 <= t_ad_data;
						when others =>	
							ad_temp <= t_ad_data;
					end case;		
					st <= st_start_con_adc_next;
				when st_start_con_adc_next =>
					t_cda <= t_cda + '1';
					st <= st_start_con_adc_next1;
				when st_start_con_adc_next1 =>
					if t_cda < channel_limit then
						st <= st_start_con_adc;
					else		
						st <= st_adc_end; 	
					end if;
				when st_adc_end =>
					st <= st_idle;
					t_can_con_adc_end <= '1';
					adc_state <= x"88";
				when st_adc_error =>
					adc_state <= x"03";
					t_can_con_adc_end <= '1';
					st <= st_idle;	
				when others =>
					st <= st_idle;
			end case;
		end if;
	end if;									
end process;

end architecture;